SBAA586 October   2023 AMC23C11 , UCC23513

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Challenge on Isolated Gate Drivers With Integrated DESAT
  6. 3System Approach With UCC23513 and AMC23C11
    1. 3.1 System Overview and Key Specification
    2. 3.2 Schematic Design
      1. 3.2.1 Circuit Schematic
      2. 3.2.2 Configure VCE(DESAT) Threshold and DESAT Bias Current
      3. 3.2.3 DESAT Blanking Time
      4. 3.2.4 DESAT Deglitch Filter
    3. 3.3 Reference PCB Layout
  7. 4Simulation and Test Results
    1. 4.1 Simulation Circuit and Results
      1. 4.1.1 Simulation Circuit
      2. 4.1.2 Simulation Results
    2. 4.2 Test Results With 3-Phase IGBT Inverter
      1. 4.2.1 Brake IGBT Test
      2. 4.2.2 Test Results on a 3-Phase Inverter With Phase to Phase Short
  8. 5Summary
  9. 6References
  10. 7Revision History

3.3 Reference PCB Layout

A reference layout is made for this circuit with an active area of 26 mm x 8.4 mm on a four-layer PCB.

GUID-20230821-SS0I-65X2-6GDZ-CQKLWWQJ7X02-low.svgFigure 3-3 Top and Bottom Sides of the Example Layout

With careful layout design placing the gate driver and the comparator on the opposite sides of the PCB, a smaller form factor is achieved, compared to a 16-pin smart gate driver's, taking advantage of their smaller package lengths. In comparison, a typical layout of ISO5451, a smart gate driver with CMOS input in a SOIC 16 package, has an active area of 20.83 mm x 12.95 mm on the PCB[10], as shown in Figure 3-4, which is about 23.5% bigger than the proposed design of UCC23513 and AMC23C11 in Figure 3-3.

GUID-20230822-SS0I-CP3P-BNZB-2MHT1BCBBXB2-low.svgFigure 3-4 Typical Layout of the Smart Gate Driver ISO5451