SBAA586 October   2023 AMC23C11 , UCC23513

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Challenge on Isolated Gate Drivers With Integrated DESAT
  6. 3System Approach With UCC23513 and AMC23C11
    1. 3.1 System Overview and Key Specification
    2. 3.2 Schematic Design
      1. 3.2.1 Circuit Schematic
      2. 3.2.2 Configure VCE(DESAT) Threshold and DESAT Bias Current
      3. 3.2.3 DESAT Blanking Time
      4. 3.2.4 DESAT Deglitch Filter
    3. 3.3 Reference PCB Layout
  7. 4Simulation and Test Results
    1. 4.1 Simulation Circuit and Results
      1. 4.1.1 Simulation Circuit
      2. 4.1.2 Simulation Results
    2. 4.2 Test Results With 3-Phase IGBT Inverter
      1. 4.2.1 Brake IGBT Test
      2. 4.2.2 Test Results on a 3-Phase Inverter With Phase to Phase Short
  8. 5Summary
  9. 6References
  10. 7Revision History

3.2.4 DESAT Deglitch Filter

R17 and C11 form a deglitch filter for the nDESAT output signal with a time constant:

Equation 9. τ  = 330 Ω × 2200 pF = 726 ns

When a TTL logic IC with a minimum low-level input of 0.8 V is followed, the deglitch time is merely 0.2 μs:

Equation 10. tDEGLITCH=-ln⁡1-0.8 V3.3 V×τ = 202 ns 

Consider the isolated comparator's internal resistance on the OUT pin is in series with R17, the tested deglitch time is about 340 ns to 380 ns in this design. Refer to test results in section 4 for details.