SBAA586 October   2023 AMC23C11 , UCC23513

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Challenge on Isolated Gate Drivers With Integrated DESAT
  6. 3System Approach With UCC23513 and AMC23C11
    1. 3.1 System Overview and Key Specification
    2. 3.2 Schematic Design
      1. 3.2.1 Circuit Schematic
      2. 3.2.2 Configure VCE(DESAT) Threshold and DESAT Bias Current
      3. 3.2.3 DESAT Blanking Time
      4. 3.2.4 DESAT Deglitch Filter
    3. 3.3 Reference PCB Layout
  7. 4Simulation and Test Results
    1. 4.1 Simulation Circuit and Results
      1. 4.1.1 Simulation Circuit
      2. 4.1.2 Simulation Results
    2. 4.2 Test Results With 3-Phase IGBT Inverter
      1. 4.2.1 Brake IGBT Test
      2. 4.2.2 Test Results on a 3-Phase Inverter With Phase to Phase Short
  8. 5Summary
  9. 6References
  10. 7Revision History

4.1.2 Simulation Results

In this simulation, the input PWM signal is set to 10 kHz, 15% duty cycle square waveform. Other conditions are set to a common application situation. Figure 4-2 is a simulation result on a DESAT protection case.

In static state, the PWM input is low, so the NAND gate output is high. UCC23513 has no input current, so the output on the GATE is also low. Thus, the isolated comparator AMC23C11's input voltage of VCIN is pulled to zero; the output OUT and the nDESAT are pulled to high.

When the input PWM signal goes to high, the NAND gate's output will shift to low, as long as the nDESAT is still in high. The UCC23513 then gets the input current and outputs high on the GATE. Then the IGBT U4 turns on and the VCE drops to the VCE(SAT). A sense current flows from GATE through R10, R12 and D1 to the collector of the IGBT U4, makes the VT1 node's voltage follow the IGBT's actual VCE and the VCIN voltage follow the VT1 voltage through the resistor divider of R13 and R14. In case the VCIN does not reach the threshold of VREF, the comparator's output OUT and the filtered output nDESAT will remain at high.

GUID-20230822-SS0I-P4KJ-T4CG-FPTC8K0SB4SX-low.svgFigure 4-2 Simulation Result of DESAT Triggered

In case of a DESAT triggered process, as shown in the above figure, when the input PWM signal (green trace in the bottom plot) goes to high, the GATE voltage of the IGBT (the red trace in the top plot) will rise up soon after, and the IGBT’s VCE sense voltage VT1 (green trace in the top plot) will also rise up. The comparator's input VCIN (the green trace in the middle plot) will then begin to rise up to follow the VT1 voltage in proportional.

Then the IGBT’s VCE (blue trace in the top plot) begins to drop. When VCE drops to below the GATE voltage, the VT1 voltage begin to follow the VCE.

Before the VCIN reaches the 1.5 V trigger threshold, set by the VREF (the red line in the middle plot), the comparator's output OUT (the blue trace in the bottom plot) will remain at high. Once VCIN reaches the trigger level, the comparator's OUT will be pulled to low with an internal propagation delay of 240 ns typically. The filtered output of nDESAT (the red trace in the bottom plot) will begin to drop, too.

As an input to the NAND gate U3, once the nDESAT triggers the negative going threshold of U3, the gate driver U1's input current will be cut off and the output GATE will be pulled down. Thus the IGBT will also be turned off and the VCE will rise up soon. This process is the DESAT protection of the circuit.

As the GATE is pulled down, the VT1 will also be pulled down and the VCIN will begin to drop. When VCIN drops to below the threshold of the comparator's input, the OUT will rise up again. This is the case with AMC23C14.

The AMC23C11 behaves exactly the same as the above process when pin 7, the LATCH input, is tied to low. When the LATCH pin is pulled to high, the output low on the comparator's OUT pin will be latched; untill the LATCH pin is pulled to low for at least 4 μs to release the latch state.