SBAA586 October 2023 AMC23C11 , UCC23513
The blanking time for DESAT monitoring, the tBLANK , is required to prevent false trig at the turn-on event of the IGBT. Capacitor C14 and resistors of R10 to R14 delay the VCE sensing signal to reach the isolated comparator's input VCIN. The delay is controlled by the charging time of C14 through the equivalent resistance REQ of the voltage divider R13 and R14:
Choose a C14 of 330 pF, then the time constant of the RC filter is:
The actual blanking time depends on the ratio of the configured VCE(DESAT) steady state threshold over the actual VCE(SAT) voltage of the IGBT in an over-current event, and can be approximated per Equation 8.
Therefore, it is important to adjust the steady state VCE(DESAT) threshold and the blanking time constant according to the individual IGBT used in the system. Refer to below table for some values with the default settings of the VCE(DESAT) steady state threshold at 8 V:
IGBT VCE(SAT) [V] | ≥ 14.5 | 12.5 | 11 | 10 | 9 | 8.5 |
tBLANK [μS] | 0.7 | 0.9 | 1.1 | 1.4 | 1.9 | 2.4 |