SBAA586 October   2023 AMC23C11 , UCC23513

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Challenge on Isolated Gate Drivers With Integrated DESAT
  6. 3System Approach With UCC23513 and AMC23C11
    1. 3.1 System Overview and Key Specification
    2. 3.2 Schematic Design
      1. 3.2.1 Circuit Schematic
      2. 3.2.2 Configure VCE(DESAT) Threshold and DESAT Bias Current
      3. 3.2.3 DESAT Blanking Time
      4. 3.2.4 DESAT Deglitch Filter
    3. 3.3 Reference PCB Layout
  7. 4Simulation and Test Results
    1. 4.1 Simulation Circuit and Results
      1. 4.1.1 Simulation Circuit
      2. 4.1.2 Simulation Results
    2. 4.2 Test Results With 3-Phase IGBT Inverter
      1. 4.2.1 Brake IGBT Test
      2. 4.2.2 Test Results on a 3-Phase Inverter With Phase to Phase Short
  8. 5Summary
  9. 6References
  10. 7Revision History

3.2 Schematic Design

Figure 3-2 shows the schematic of a design with a 15-V unipolar supply to drive an IGBT. With some minor changes this design can be fit to a 12-V power supply design for power MOSFETs driving or bipolar power supply applications. See reference design TIDA-00448 for more details.

Resistors R9 through R14 and the high voltage diode D1 are used to sense the actual VCE of the IGBT during the turn-on period and scale it according to the reference voltage VREF of the isolated comparator AMC23C11. R10 and R11 are in parallel to spilit the power dissipation.

The capacitor C14 in parallel to R14 sets a blanking time to avoid false trig during the IGBT turn-on. A 5.1-V Zener diode D2 is added as an option to suppress possible high voltage spikes due to the IGBT switching. Note that the internal capacitance of D2 will be in parallel to C14 and contribute to the blanking time. In our tests we did not assemble this D2. A fast switching diode D1 with low internal capacitance is recommended to avoid false DESAT trigger and minimize the blanking time required.

The low voltage side uses a 3.3-V supply to directly interface the I/O level of popular MCUs, like the C2000TM and the Sitara MCUs. R6 and C11 set a deglitch delay (default 0.2 μs) for the comparator's output, in case of the LATCH is not activated.