SBAA586 October   2023 AMC23C11 , UCC23513

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Challenge on Isolated Gate Drivers With Integrated DESAT
  6. 3System Approach With UCC23513 and AMC23C11
    1. 3.1 System Overview and Key Specification
    2. 3.2 Schematic Design
      1. 3.2.1 Circuit Schematic
      2. 3.2.2 Configure VCE(DESAT) Threshold and DESAT Bias Current
      3. 3.2.3 DESAT Blanking Time
      4. 3.2.4 DESAT Deglitch Filter
    3. 3.3 Reference PCB Layout
  7. 4Simulation and Test Results
    1. 4.1 Simulation Circuit and Results
      1. 4.1.1 Simulation Circuit
      2. 4.1.2 Simulation Results
    2. 4.2 Test Results With 3-Phase IGBT Inverter
      1. 4.2.1 Brake IGBT Test
      2. 4.2.2 Test Results on a 3-Phase Inverter With Phase to Phase Short
  8. 5Summary
  9. 6References
  10. 7Revision History

3.1 System Overview and Key Specification

Figure 3-1 shows a simplified block diagram of the proposed circuit. Here, we use an IGBT as the power switch; and the design is also appropriate for a power MOSFET with some minor changes.

GUID-20230821-SS0I-BXCJ-8VDG-GQTNH7MG9CR0-low.svg Figure 3-1 Simplified System Block Diagram

A NAND gate is used to realize a function to monitor the VCE only when the PWM input is high. The chip disables the gate driver’s input, once the sensed VCE exceeds the DESAT threshold VREF. Table 3-1 shows the key parameters of the application circuit.

Table 3-1 Key System Parameters of the Design
ParameterValueComment
Reinforced isolated gate driverUCC23513 or UCC23511(1)

6-pin DWY (SO-6) package, see figure 2-1.

B version to support 8-V UVLO.

Isolated gate drive supply,

VDD

+15 V (IGBT), +12 V (FET)Unipolar supply
DESAT VCE threshold voltage,

VCE(DESAT)

8.0 VConfigurable.

See section 3.2.2.

DESAT bias current,

iBIAS(DESAT)

5.5 mAConfigurable.

See section 3.2.2.

DESAT blanking filter time constant, tBLANK

0.8 μs

Valid for VCE(SAT)=12.5V. Configurable.

See equation 8 and table 3-2 in section 3.2.3.

DESAT deglitch filter

delay, tDEGLITCH

0.2 μsConfigurable.

See equation 10 in section 3.2.3.

DESAT latch with resetEnabledCan be disabled.
DESAT reaction time(2)

About 1.1 μs to 1.6 μs

By default configuration.

Refer to test results.

PCB size without connectors26 mm x 8.4 mm
Note: (1) UCC23511 is a 1.5-A source, 2-A sink device in same package as UCC23513.

(2) For clear and simple description on the protection process, in this application note, we use 'DESAT reaction time' for the period from the sensed power switch's current reaches to the set trigger level to the point the current begin to drop due to the DESAT protection.

The UCC2351x series can be used to drive power switches of IGBT, SiC, or MOSFET. Both UCC23511 and UCC23513 are offered in a stretched SO-6 package of 7.50 mm x 4.68 mm body size, with greater than 8.5 mm creepage and clearance. Both devices bring significant performance and reliability upgrades over the standard optocoupler based gate drivers while maintaining pin-to-pin compatibility. Their performance advantages include high CMTI, low propagation delay, and small pulse width distortion. The input stage is an emulated diode (ediode) which provides long term reliability and excellent aging characteristics over the traditional LEDs.

The AMC23C11 isolated comparator comes in a 8-pin wide-body SOIC package with a body size of 5.85 mm × 7.50 mm. The device compares the input voltage on the VIN pin against a threshold, adjustable from 20 mV to 2 V, and set by an internal 100-μA reference current and an external resistor. The open-drain output is actively pulled to low when the input voltage VIN is higher than the reference value VREF. When VIN drops below the trip threshold, the device’s behavior is determined by the LATCH pin:

  • When the LATCH pin is pulled to low, the device is set to transparent mode, allowing the output state to change and follow the input signal with respect to the trip threshold.
  • When the LATCH pin is pulled to high, the device is set to latch mode. Once an out-of-range condition is detected, the OUT pin is pulled to low and latched, until the LATCH pin is pulled to low for at least 4 μs to release this latch.

The isolation barrier in AMC23C11 is highly resistant to magnetic interference, and certified to provide a reinforced galvanic isolation of up to 5 kVRMS.