Understanding the mechanisms involved in designing high speed analog-to-digital converter frontends, is sometimes like an art all in its own. Simply plopping a balun down and drawing two trace lines from the balun’s secondary outputs to the ADC’s inputs is not something that is recommended in any high-speed analog receiver frontend design. Baluns are notorious for being parasitic sensitive on bandwidth (BW), along with other nuisances. Here in this paper, we reveal a few ways to get the most out of your passive analog input design using a balun. The added benefit, is that you do not need a costly balun nor a costly attenuation pad between the two devices to achieve the BW you are looking for. So sit back, grab a beverage, as we unveil the fine art of tuning for BW and distortion.
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Before opening the CAD SW program to start on your PCB layout, we assume you have already decided on both the ADC you plan to use and the BW intended for your application. Now you need to decide, if the passive frontend is right for your design. Assuming again, you do not need to DC couple, that is, sample the DC frequency bin. Because a balun does not require an additional power supply, the benefits of using a balun include lower overall power consumption, and smaller board space requirements. Additionally, with no extra supply to contend with, a balun does not add noise to the overall RF signal chain that leads up to the ADC. This, in turn, means no degradation in SNR (signal-to-noise ratio) or NSD (noise spectral density) can occur.
Once established, a balun must be chosen, and the choices are numerous. When choosing a balun, the suggestion is to first look at your BW requirements. Choose a balun that has a bit more bandwidth than what is required so that the balun acts more like a window than a door. This is especially important at those higher frequency applications. See Figure 1-1. Shown are two different baluns used in the same application with the ADC3669, 16-bit, dual channel ADC. Even though both baluns are rated for the same BW, they can ultimately respond differently due to the combination of the ADC’s varying input impedance due to the ADC’s internal sample network, as well as the PCB trace parasitics. Notice that with no match applied with either balun, the BW falls quite rapidly, as noted in the two points described previously.
A few other nuggets to think about during the balun down-selection process and before you go off and start simulating. Take a close look at the balun’s PCB footprint and layout recommendation in the data sheet, there is a reason why it is the way it is. The recommendation is to follow these recommendations exactly, unless you want to inadvertently make the balun respond differently. The balun was characterized using this footprint both for the data sheet collection and measuring the s-parameters, and can only perform up to spec under these circumstances. Which leads me to another thought, sometimes our balun vendors use the balun test board to measure the s-parameters, and do not de-embed the connectors nor the traces on the test board. So BW beware!
Lastly, start to understand the balun’s phase imbalance over your specific BW. The poorer the balun’s inherent phase imbalance the worse even order distortion (HD2 or second harmonic distortion) the ADC can manifest. If HD2 is important to your frequency planning application, it is recommended to pick a balun with good phase imbalance. There is really no good guide on this, as each ADC can also have the sensitivity to phase differences across its useable frequency range. Typically choosing a balun that has <5degrees of phase imbalance over your application operating BW can be a good start. This can add little to the aggregate even order distortion already existing in your RF signal chain lineup. For more information on balun phase imbalance and its impact to even order distortion, see the reference link. Figure 1-2 shows the difference between the same two matched baluns scenarios again, and impact it has on even order distortion using the ADC3669. Notice the HD3, odd order distortion, or third harmonic response is relatively the same across frequency and has no impacted differences.
Over the years, we have seen many attempts to simulate and get the balun match perfected. After weeks to months of simulation and trying to understand some level of PCB parasitic, the match does not quite work out when the PCB design is fabricated. The recommendation is to start the design process differently, use the following topology as shown in Figure 2-1. This can give you a great sandbox to play in using any components you wish to complete the match. Wonder if all of this effort and tradeoffs are actually worth it, the suggestion is to refer back to Figure 1-1. The following section describes each component to know the need or function within the input matching network to the ADC.
C1/C2: typically a 0.1uF, blocks DC from being fed into the balun or transformer. Some balun designs lead to ground and or DC can aggravate the balun’s function leading to poor performance. So, that is what they are for, put them in.
R1: allows for back termination near the outputs of the balun after the DC blocking capacitors, not always needed, if your trace lengths are long enough you can need this component. Assuming no perfect match across the band of interest is something that cannot be achieved, you can need to back terminate to handle any standing waves that can accumulate as the imperfect match rolls back and forth across your frequency range.
R2/R3/R4: This allows for various matching techniques to be employed. These three components are the heart of the match and can take the form in several combinations to solve the balun or ADC matching conundrum. For widest band matches these three components generally are configured as a matching pad. This helps to dissolve the standing waves between the balun and ADC providing for a “stiff” 50ohm impedance that is generally needed by both devices. Though these are represented as resistors, these components can take the form of capacitors and or inductors as well.
C3: this capacitor, typically a 0.1uF, ties the center point of the R3s together and allows for an AC current path. This is also a good idea because when over-ranging the ADC’s input full scale, this allows for this AC current to go somewhere…you are welcome. Side note: this capacitor can also be located at R5 instead.
R5: allows back termination, on the opposite side near the ADC’s inputs, and is again not always necessary. This provides the same function as R1 but from the opposite perspective to help resolve standing waves that can accumulate. Typically, the need for R1 and or R5 are required when trace connections are 300mils in length or more.
R6: these are your kickback components. These are typically in the form of resistors but in some cases inductors or low-Q ferrite beads can help snub any residual charge kickback that comes back onto the analog input network from the internal sampling circuit in the ADC. These component placeholders are essential when using unbuffered ADCs.
Again, be weary if you just plan to run two traces from the output of the balun to the inputs of the ADC. Even if you collect s-parameters, simulate, and prove the output out to your colleagues, this can prove to be costly unless you have previous experience with the balun and ADC combo.