SBAK019 May 2024 ADC3683-SP
The ADC3683-SP is fabricated in the TI CMOS C021(C021, 65nm process with a Back-End-Of-Line (BEOL) stack consisting of eight levels of standard thickness aluminum metal. The total stack height from the surface of the passivation to the silicon surface is 20.7μm based on nominal layer thickness. Accounting for energy loss through the 1mil thick Aramica beam port window, the 40mm air gap and the BEOL stack over the ADC3683-SP, the effective LET (LETEFF) at the surface of the silicon substrate, the depth, and the ion range was determined with the SEUSS 2020 software that was provided by the Texas A&M University Cyclotron Institute and based on the latest SRIM-2013models (4, 5). Table 5-1 lists the results.
Ion Type | Angle of Incidence (°) | RangeEFF in Silicon (µm) | LETEFF (MeV × cm2/mg) |
---|---|---|---|
141Pr | 30 | 68.1 | 78.67 |
141Pr | 0 | 81.9 | 67.45 |
109Ag | 30 | 63.5 | 59.82 |
109Ag | 0 | 76.6 | 51.12 |
63Cu | 0 | 102 | 21.44 |