SBAK021 December   2024 AFE7950-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Test Setup and Procedures
  9. 6Destructive Single-Event Effects (DSEE)
  10. 7Single-Event Effects (SEE)
  11. 8Event Rate Calculations
  12. 9References

2 Single-Event Effects

The primary concern of interest for the AFE7950-SP is the robustness against Single-Event Latch-up (SEL) and Single -Event Functional Interrupt (SEFI)

In CMOS technologies, such as the TSMC's 28nm CMOS (C28) process used on the AFE7950-SP, the CMOS circuitry introduces a potential for SEL susceptibility. SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts). The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current). This current between power and ground persists or is latched until power is removed, the device is reset, or until the device is destroyed by the high-current state. The AFE7950-SP was tested for SEL using the AFE7950EVM which operates the device at recommended power supply voltages. The device exhibits no SEL with heavy-ions up to LETEFF = 70 MeV·cm2/mg at a flux ≈ 105 ions/cm2·s, fluence of ≈ 107 ions/cm2, and a die temperature of 125°C, using Pr.

The AFE7950-SP was characterized for SEUs at fluxes between 102 ions/cm2·s and 103 ions/cm2·s and with a fluence up to 106 ions/cm2 at ambient room temperature. More details regarding single event upsets and functional interupts can be found in Section 7.