The DAC9881 is an 18-bit, single-channel, voltage-output digital-to-analog converter (DAC). The device features 18-bit monotonicity, excellent linearity, very low-noise, and fast settling time. The on-chip precision output amplifier allows for a rail-to-rail output swing to be achieved over the full supply range of 2.7 V to 5.5 V.
The device supports a standard serial peripheral interface (SPI) capable of operating with input data clock frequencies of up to 50 MHz. The DAC9881 requires an external reference voltage to set the output range of the DAC channel. A programmable power-on reset circuit is also incorporated into the device to make sure that the DAC output powers up at zero-scale or midscale, and remains there until a valid write command.
Additionally, the DAC9881 has the capability to function in either unipolar straight binary or two's complement mode. The DAC9881 provides low-power operation. To further save energy, power-down mode can be achieved by accessing the PDN pin, thereby reducing the current consumption to 25 µA at 5 V. Power consumption is 4 mW at 5 V, reducing to 125 µW in power-down mode.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC9881 | VQFN (24) | 4.00 mm × 4.00 mm |
Changes from B Revision (March 2016) to C Revision
Changes from A Revision (August 2008) to B Revision
Changes from * Revision (May 2008) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | SCLK | I | SPI bus serial clock input |
2 | SDI | I | SPI bus serial data input |
3 | LDAC | I | Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. It is recommended to connect this pin to IOVDD through a pullup resistor. |
4 | AGND | I | Analog ground |
5 | AVDD | I | Analog power supply |
6 | VREFL-S | I | Reference low input sense |
7 | VREFH-S | I | Reference high input sense |
8 | VOUT | O | Output of output buffer |
9 | RFB | I | Feedback resistor connected to the inverting input of the output buffer |
10 | VREFL-F | I | Reference low input force |
11 | VREFH-F | I | Reference high input force |
12 | NC | — | Do not connect |
13 | NC | — | Do not connect |
14 | RSTSEL | I | Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data = 20000h. If RSTSEL = DGND, then register data = 00000h. |
15 | GAIN | I | Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD. |
16 | USB/BTC | I | Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in two's complement format when the pin is connected to DGND. |
17 | RST | I | Reset input (active low). Logic low on this pin causes the device to perform a reset. |
18 | PDN | I | Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT pin connects to AGND through a 10-kΩ resistor. |
19 | CS | I | SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is high, SDO is in a high-impedance state. It is recommended to connect this pin to IOVDD through a pullup resistor. |
20 | SDOSEL | I | SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register are shifted out from the SDO pin; this is Daisy-Chain mode for daisy-chained communication. |
21 | AVDD | I | Analog power supply. Must be connected to pin 5. |
22 | DGND | I | Digital ground |
23 | SDO | O | SPI bus serial data output. Refer to the timing diagrams for further detail. |
24 | IOVDD | I | Interface power. Connect to 1.8 V for 1.8-V logic, 3 V for 3-V logic, and to 5 V for 5-V logic. |
Thermal pad | — | The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. |