SBAS528 Data sheet

SBAS528D June 2013 – December 2021 DAC7760 , DAC8760

PRODUCTION DATA

7.10 Typical Characteristics

at T_A = 25°C (unless otherwise noted)

Figure 7-3 REFOUT vs Temperature

Figure 7-5 REFOUT vs Load Current

Figure 7-7 REFOUT Noise PSD vs Frequency

Figure 7-9 REFOUT Transient vs Time

Figure 7-11 AIDD vs AVDD

Figure 7-13 Internal DVDD vs Load Current

Figure 7-15 VOUT TUE vs Code (Unipolar Outputs)

Figure 7-17 VOUT TUE vs Temperature

Figure 7-19 VOUT INL vs Code (Unipolar Outputs)

Figure 7-21 VOUT INL vs Temperature

Figure 7-23 VOUT DNL vs Code (Unipolar Outputs)

Figure 7-25 VOUT DNL vs Temperature

Figure 7-27 VOUT Full-Scale Error vs Temperature

Figure 7-29 Bipolar Zero Error vs Temperature

Figure 7-31 Zero-Scale Error vs Temperature

Figure 7-33 VOUT (Zero-Scale) vs Load Current
(Source or Sink)

Figure 7-35 BP10V Falling

Figure 7-37 VOUT Settling Time vs LOAD
(100 pF Between VOUT and CMP Pins)

Figure 7-39 VOUT Power-On Glitch

Figure 7-41 VOUT Noise PSD vs Frequency

Figure 7-43 VOUT Hi-Z Leakage Current vs Voltage

Figure 7-45 AVDD PSRR for VOUT

Figure 7-47 IOUT TUE vs Code (0 mA to 20 mA)

Figure 7-49 IOUT TUE vs Temperature (Internal R_SET)

Figure 7-51 IOUT TUE vs Supply (Internal R_SET)

Figure 7-53 IOUT INL vs Code (0 mA to 24 mA)

Figure 7-55 IOUT INL vs Code (4 mA to 20 mA)

Figure 7-57 IOUT INL vs Temperature (External R_SET)

Figure 7-59 IOUT INL vs Supply (External R_SET)

Figure 7-61 IOUT DNL vs Code (0 mA to 20 mA)

Figure 7-63 IOUT DNL vs Temperature (Internal R_SET)

Figure 7-65 IOUT DNL vs Supply (Internal R_SET)

Figure 7-67 IOUT Full-Scale Error vs Temperature

Figure 7-69 IOUT Gain Error vs Temperature

Compliance voltage headroom is defined as the drop from AVDD pin to the IOUT pin.

Figure 7-71 IOUT vs Compliance Headroom Voltage

Figure 7-73 4-mA to 20-mA Falling

Figure 7-75 IOUT Output Enable Glitch

Figure 7-77 IOUT Noise PSD vs Frequency

Figure 7-79 IOUT Hi-Z Leakage Current vs Voltage

Figure 7-4 Internal Reference Temperature Drift Histogram

Figure 7-6 REFOUT vs AVDD

Figure 7-8 Internal Reference, Peak-to-Peak Noise
(0.1 Hz to 10 Hz)

Figure 7-10 AIDD or AISS vs AVDD or AVSS

Figure 7-12 DIDD vs External DVDD

Figure 7-14 Internal DVDD PSRR vs Frequency

Figure 7-16 VOUT TUE vs Code

Figure 7-18 VOUT TUE vs Supply

Figure 7-20 VOUT INL vs Code

Figure 7-22 VOUT INL vs Supply

Figure 7-24 VOUT DNL vs Code

Figure 7-26 VOUT DNL vs Supply

Figure 7-28 Offset Error vs Temperature

Figure 7-30 Gain Error vs Temperature

Figure 7-32 VOUT (Full-Scale) vs Load Current (Source or Sink)

Figure 7-34 BP10V Rising

Figure 7-36 VOUT Settling Time vs Load
(No Compensation Capacitor)

Figure 7-38 VOUT Settling Time vs LOAD
(470 pF Between VOUT and CMP Pins)

Figure 7-40 VOUT Digital-to-Analog Glitch

Figure 7-42 VOUT, Peak-to-Peak Noise (0.1 Hz to 10 Hz)

Figure 7-44 VOUT Short-Circuit Current vs Temperature

Figure 7-46 IOUT TUE vs Code (0 mA to 24 mA)

Figure 7-48 IOUT TUE vs Code (4 mA to 20 mA)

Figure 7-50 IOUT TUE vs Temperature (External R_SET)

Figure 7-52 IOUT TUE vs Supply (External R_SET)

Figure 7-54 IOUT INL vs Code (0 mA to 20 mA)

Figure 7-56 IOUT INL vs Temperature (Internal R_SET)

Figure 7-58 IOUT INL vs Supply (Internal R_SET)

Figure 7-60 IOUT DNL vs CODE (0 mA to 24 mA)

Figure 7-62 IOUT DNL vs Code (4 mA to 20 mA)

Figure 7-64 IOUT DNL vs Temperature (External R_SET)

Figure 7-66 IOUT DNL vs Supply (External R_SET)

Figure 7-68 IOUT Offset Error vs Temperature

Compliance voltage headroom is defined as the drop from AVDD pin to the IOUT pin.

Figure 7-70 Compliance Headroom Voltage⁽¹⁾ vs Temperature

Figure 7-72 4-mA to 20-mA Rising

Figure 7-74 IOUT Power-On Glitch

Figure 7-76 IOUT Digital-to-Analog Glitch

Figure 7-78 IOUT Peak-to-Peak Noise vs Time (0.1 Hz to 10 Hz)

Figure 7-80 IOUT PSRR vs Frequency