SBAS649B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
MODE2 uses a single DAC channel fed by four 12-bit LVDS data buses resulting in 48 LVDS lanes total. Due to the high bit rate, each 12-bit LVDS bus has its own dual-data rate (DDR) clock to maximize timing windows. This mode allows the maximum data rate into a single DAC. Table 7-6 shows the LVDS bus, data clock and strobe assignments for each channel. Figure 7-17 shows the block diagram for this mode for further understanding, including the signal assignments.
DAC CHANNEL | LVDS BUSES | DATA CLOCKS | STROBE USED |
---|---|---|---|
A or B | A, B, C, D | DACLK, DBCLK, DCCLK, DDCLK | DASTR, DBSTR, DCSTR, DDSTR |
Figure 7-18 shows the functional timing diagram for MODE2. Four 12-bit buses are used (A, B, C and D) to send data to the DAC. There is no strict timing skew requirement between LVDS buses (e.g. A to B or A to D) as long as the internal FIFOs maintain sufficient offset between read and write pointers.
Having the LVDS banks staggered as shown in Figure 7-18 allows the data from each bank to arrive as it is needed and results in minimal latency from each bank. If the LVDS banks have their clocks aligned, then the data on bank 3 is provided to the chip 3 DAC clocks before it is needed.