SBAS649B June   2021  – June 2022 DAC12DL3200

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
      4. 7.3.4 Multi-Device Synchronization (SYSREF+/-)
        1. 7.3.4.1 DACCLK Domain Synchronization
        2. 7.3.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 Alarms
    4. 7.4 Device Functional Modes
      1. 7.4.1 Direct Digital Synthesis (DDS) Mode
        1. 7.4.1.1 NCO Gain Scaling
        2. 7.4.1.2 NCO Phase Continuous Operation
        3. 7.4.1.3 Trigger Clock
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Operation
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 SPI Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
7.3.3.5.2 FIFO Delay Handling

Data from the LVDS banks are latched into the write side of the FIFO using the LVDS clock. The user must set FIFO_DLY to an appropriate value to ensure that the data is read away from the point where it is changing. To help with this, the FIFO_DLY_R* registers provide the user with an approximate FIFO_DLY setting that would result in the data being sampled just as it arrives under current conditions.

The number of usable settings for FIFO_DLY is determined by LVDS_MODE and DCM_EN as shown in Figure 7-19.

GUID-20200917-CA0I-Q411-2L5D-SX4KMBVPXZV5-low.gifFigure 7-19 FIFO_DLY Circles

In the above picture we will assume that if FIFO_DLY=1, it would result in the data being sampled just as the input latch is changing. Ideally, FIFO_DLY_R* would report “1” in this condition. In reality, this is not a precise measurement and it will only report a value close to this setting. If minimum latency is not a concern, it may be sufficient to just select a FIFO_DLY value on the opposite side of the circle from the FIFO_DLY_R* value.

Setting FIFO_DLY to a value before (counter-clockwise from) the FIFO_DLY_R* value will result in the lowest possible latency. For example, if running in LVDS_MODE=2, with FIFO_DLY_R*=1, a value of 30 may be an appropriate low latency setting while a value of 4 would be a high latency setting.

If the goal is to create a system with minimum latency, the user will need to characterize the system to find the optimal value of FIFO_DLY that will consistently work across process, voltage and temperature (PVT). The less variation that exists between the SYSREF, LVDSCLK, and DEVCLK, the tighter the FIFO_DLY can be set.

Note that if the LVDS strobe is used to align the DACCLK domain side of the FIFO instead of SYSREF, additional margin should be added to FIFO_DLY to allow for inconsistent setup of the FIFO from one alignment to the next. It is not possible to have deterministic latency using the LVDS strobe.

To help with system characterization, underflow and overflow alarms are provided in FIFO_ALM. It is important to realize toggling data must be provided on the input for these alarms to work. Constant input data will not generate alarms. See FIFO Over/Under Flow Alarming.

To characterize the FIFO_DLY for minimum latency with SYSREF:

  1. Align the system using SYSREF (refer to section Startup Procedure with LVDS Input)
  2. Read the FIFO_DLY_R* values to determine a reasonable starting point for FIFO_DLY characterization.
  3. Set a FIFO_DLY value that is near the sampling point. For example, if FIFO_DLY_R*=1, a setting for 30 might be a good starting point.
  4. Characterize the system over PVT and monitor FIFO_ALM for any alarms.
  5. If alarms occurred, move FIFO_DLY one setting counter-clockwise and repeat from step 3. If no alarms occurred, move FIFO_DLY one setting clockwise and repeat from step 3. The goal is to determine the tightest setting that will not cause alarms.

It is important to understand that there will be some number of FIFO_DLY settings that are unusable. In 4-banks per DAC mode this may be as many as 4 settings. Reducing the LVDS rate will reduce the number of invalid FIFO_DLY settings.