SBAS649B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
MODE1 uses one 12-bit LVDS data bus per channel. One dual-data rate (DDR) clock is used for each 12-bit LVDS data bus resulting in two total data clocks. This mode allows one fourth of the maximum sampling rate of the DAC. Table 7-5 shows the LVDS bus, data clock and strobe assignments for each channel. Figure 7-15 shows the block diagram for this mode for further understanding, including the signal assignments.
DAC CHANNEL | LVDS BUSES | DATA CLOCKS | STROBE USED |
---|---|---|---|
A | A | DACLK | DASTR |
B | C | DCCLK | DCSTR |
Figure 7-16 shows the functional timing diagram for MODE1. Two 12-bit buses are used, with bus A for DAC channel A data and bus C for DAC channel B data. There is no strict timing skew requirement between LVDS buses (e.g. A to C) as long as the internal FIFOs maintain sufficient offset between read and write pointers.