SBAS649B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
A linear frequency chirp signal with 200 MHz BW, 146.5 MHz/μs and 1.36 μs repetition rate centered at 2.4 GHz was input to the ADC12DL3200. Analog input signal is shown in Figure 8-2. The signal after loopback at the DAC12DL3200 output is shown in Figure 8-3, and matches well the analog input.
The DAC12DL3200 and ADC12DL3200 latency depend on mode and are 30.5 clock cycles for the DAC and 26 clock cyles for the ADC. At 3.2 GHz, one clock period is 313 ps and therefore the total DAC and ADC latency is 17.7 ns. The latency through the FPGA depends on the FPGA firmware. With significant optimization, a latency of < 20 ns (without signal processing) is possible. To demonstrate an optimized latency, the ADC MSB output was looped back to the DAC MSB input with an latency optimized FPGA firmware. Figure 8-4 shows the ADC input to DAC output, with a latency of 32.6 ns, meeting the system design requirement.