SBAS738A June   2018  – October 2018 ISO224

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Input Clamp Protection Circuit
      3. 8.3.3 Isolation Channel Signal Transmission
      4. 8.3.4 Fail-Safe Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr, tf Rise time, fall time ISO224B on OUTP, OUTN 1.5 µs
ISO224A on OUTP, OUTN 2 µs
IN to OUTP, OUTN signal delay (50% – 10%) ISO224B, unfiltered output, see Figure 1 1.5 2 µs
ISO224A, unfiltered output, see Figure 1 1.9 2.9
IN to OUTP, OUTN signal delay (50% – 50%) ISO224B, unfiltered output, see Figure 1 2.2 2.7 µs
ISO224A, unfiltered output, see Figure 1 2.8 3.8
IN to OUTP, OUTN signal delay (50% – 90%) ISO224B, unfiltered output, see Figure 1 3 3.5 µs
ISO224A, unfiltered output, see Figure 1 3.8 4.8
tAS Analog startup time VDD1 step to 4.5 V with VDD2 ≥ 4.5 V,
to OUTP, OUTN valid, 0.1% settling		 250 µs
ISO224 tim_bas738.gifFigure 1. Delay Time Test Waveforms