8.1.1 Start-Up Sequence

Table 62 lists the recommended start-up sequence for a 500-MSPS, Nyquist 2 operation with DDC mode 8 enabled.

Table 63 lists the recommended start-up sequence for a 500-MSPS, Nyquist 2, 2x interleaved dual ADC operation.

8.1.2 Hardware Reset

Figure 130 shows the timing information for the hardware reset.

Figure 130. Hardware Reset Timing Diagram

8.1.3 Frequency Planning

The ADS54J64 uses an architecture where the ADCs are 2x interleaved followed by a digital decimation by 2. The 2x interleaved and decimation architecture comes with a unique advantage of improved linearity resulting from frequency planning. Frequency planning refers to choosing the clock frequency and signal band appropriately such that the harmonic distortion components, resulting from the analog front-end (LNA, PGA), can be made to fall outside the decimation filter pass band. In absence of the 2x interleave and decimation architecture, these components alias back in band and limit the performance of the signal chain. For example, for f_CLK = 983.04 MHz and f_IN = 184.32 MHz:

Second-order harmonic distortion (HD2) = 2 × 184.32 = 368.64 MHz

Pass band of the 2x decimation filter = 0 MHz to 245.76 MHz (0 to f_CLK / 4)

The second-order harmonic performance improves by the stop-band attenuation of the filter (approximately 40 dBc) because the second-order harmonic frequency is outside the pass band of the decimation filter.

Figure 131 shows the harmonic components (HD2–HD5) that fall in the decimation pass band for the input clock rate (f_CLK) of the 983.04-MHz and 100-MHz signal band around the center frequency of 184.32 MHz.

NOTE:

f_CLK = 983.04 MHz, signal band = 134.32 MHz to 234.32 MHz.

Figure 131. In-Band Harmonics for a Frequency Planned System

As shown in Figure 131, both HD2 and HD3 are completely out of band. HD4 and HD5 fall in the decimation pass band for some frequencies of the input signal band.

Through proper frequency planning, the specifications of the ADC antialias filter can be relaxed.

8.1.4 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors (as shown in Equation 3): the quantization noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.

Equation 3.

Equation 4 calculates the SNR limitation resulting from sample clock jitter:

Equation 4.

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (100 f_S for the ADS54J64) that is set by the noise of the clock input buffer and the external clock jitter. Equation 5 calculates T_Jitter:

Equation 5.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input; a faster clock slew rate also improves the ADC aperture jitter.

The ADS54J64 has a thermal noise of approximately 70 dBFS and an internal aperture jitter of 100 f_S.

8.1.5 ADC Test Pattern

The ADS54J64 provides several different options to output test patterns instead of the actual output data of the ADC in order to simplify debugging of the JESD204B digital interface link. Figure 132 shows the output data path.

Figure 132. ADC Test Pattern

8.2.1 Design Requirements

By using the simple drive circuit of Figure 133 (when the amplifier drives the ADC) or Figure 46 (when transformers drive the ADC), uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

8.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves the common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin, as shown in Figure 133, is recommended to damp out ringing caused by package parasitics.

8.2.3 Application Curves

Figure 134 and Figure 135 show the typical performance at 190 MHz and 230 MHz, respectively.

fIN = 190 MHz, AIN = –1 dBFS, SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (non 23)

Figure 134. FFT for 190-MHz Input Signal

fIN = 230 MHz, AIN = –1 dBFS, SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (non 23)

Figure 135. FFT for 230-MHz Input Signal