SBAS841 October   2017 ADS54J64

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Typical Characteristics: DDC Bypass Mode
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
    12. 6.12 Typical Characteristics: Dual ADC Mode
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuit
      3. 7.3.3 Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Functions
        1. 7.4.1.1  Numerically Controlled Oscillators (NCOs) and Mixers
        2. 7.4.1.2  Decimation Filter
          1. 7.4.1.2.1 Stage-1 Filter
          2. 7.4.1.2.2 Stage-2 Filter
        3. 7.4.1.3  Mode 0: Decimate-by-4 With IQ Outputs and fS / 4 Mixer
        4. 7.4.1.4  Mode 1: Decimate-by-4 With IQ Outputs and 16-Bit NCO
        5. 7.4.1.5  Mode 2: Decimate-by-4 With Real Output
        6. 7.4.1.6  Mode 3: Decimate-by-2 Real Output With Frequency Shift
        7. 7.4.1.7  Mode 4: Decimate-by-4 With Real Output
        8. 7.4.1.8  Mode 6: Decimate-by-4 With IQ Outputs for Up to 110 MHz of IQ Bandwidth
        9. 7.4.1.9  Mode 7: Decimate-by-4 With Real Output and Zero Stuffing
        10. 7.4.1.10 Mode 8: DDC Bypass Mode
        11. 7.4.1.11 Averaging Mode
        12. 7.4.1.12 Overrange Indication
    5. 7.5 Programming
      1. 7.5.1 JESD204B Interface
      2. 7.5.2 JESD204B Initial Lane Alignment (ILA)
      3. 7.5.3 JESD204B Frame Assembly
      4. 7.5.4 JESD Output Switch
        1. 7.5.4.1 SerDes Transmitter Interface
        2. 7.5.4.2 SYNCb Interface
        3. 7.5.4.3 Eye Diagram
      5. 7.5.5 Device Configuration
        1. 7.5.5.1 Details of the Serial Interface
          1. 7.5.5.1.1 Register Initialization
        2. 7.5.5.2 Serial Register Write
        3. 7.5.5.3 Serial Read
    6. 7.6 Register Maps
      1. 7.6.1 Register Map
        1. 7.6.1.1 Register Description
          1. 7.6.1.1.1 GLOBAL Page Register Description
            1. 7.6.1.1.1.1 Register 00h (address = 00h) [reset = 0h], GLOBAL Page
            2. 7.6.1.1.1.2 Register 04h (address = 04h) [reset = 0h], GLOBAL Page
            3. 7.6.1.1.1.3 Register 11h (address = 11h) [reset = 0h], GLOBAL Page
            4. 7.6.1.1.1.4 Register 12h (address = 12h) [reset = 0h], GLOBAL Page
            5. 7.6.1.1.1.5 Register 13h (address = 13h) [reset = 0h], GLOBAL Page
          2. 7.6.1.1.2 DIGTOP Page Register Description
            1. 7.6.1.1.2.1  Register 64h (address = 64h) [reset = 0h], DIGTOP Page
            2. 7.6.1.1.2.2  Register 8Dh (address = 8Dh) [reset = 0h], DIGTOP Page
            3. 7.6.1.1.2.3  Register 8Eh (address = 8Eh) [reset = 0h], DIGTOP Page
            4. 7.6.1.1.2.4  Register 8Fh (address = 8Fh) [reset = 0h], DIGTOP Page
            5. 7.6.1.1.2.5  Register 90h (address = 90h) [reset = 0h], DIGTOP Page
            6. 7.6.1.1.2.6  Register 91h (address = 91h) [reset = 0h], DIGTOP Page
            7. 7.6.1.1.2.7  Register A5h (address = A5h) [reset = 0h], DIGTOP Page
            8. 7.6.1.1.2.8  Register A6h (address = A6h) [reset = 0h], DIGTOP Page
            9. 7.6.1.1.2.9  Register ABh (address = ABh) [reset = 0h], DIGTOP Page
            10. 7.6.1.1.2.10 Register ACh (address = ACh) [reset = 0h], DIGTOP Page
            11. 7.6.1.1.2.11 Register ADh (address = ADh) [reset = 0h], DIGTOP Page
            12. 7.6.1.1.2.12 Register AEh (address = AEh) [reset = 0h], DIGTOP Page
            13. 7.6.1.1.2.13 Register B7h (address = B7h) [reset = 0h], DIGTOP Page
            14. 7.6.1.1.2.14 Register 8Ch (address = 8Ch) [reset = 0h], DIGTOP Page
          3. 7.6.1.1.3 ANALOG Page Register Description
            1. 7.6.1.1.3.1  Register 6Ah (address = 6Ah) [reset = 0h], ANALOG Page
            2. 7.6.1.1.3.2  Register 6Fh (address = 6Fh) [reset = 0h], ANALOG Page
            3. 7.6.1.1.3.3  Register 71h (address = 71h) [reset = 0h], ANALOG Page
            4. 7.6.1.1.3.4  Register 72h (address = 72h) [reset = 0h], ANALOG Page
            5. 7.6.1.1.3.5  Register 93h (address = 93h) [reset = 0h], ANALOG Page
            6. 7.6.1.1.3.6  Register 94h (address = 94h) [reset = 0h], ANALOG Page
            7. 7.6.1.1.3.7  Register 9Bh (address = 9Bh) [reset = 0h], ANALOG Page
            8. 7.6.1.1.3.8  Register 9Dh (address = 9Dh) [reset = 0h], ANALOG Page
            9. 7.6.1.1.3.9  Register 9Eh (address = 9Eh) [reset = 0h], ANALOG Page
            10. 7.6.1.1.3.10 Register 9Fh (address = 9Fh) [reset = 0h], ANALOG Page
            11. 7.6.1.1.3.11 Register AFh (address = AFh) [reset = 0h], ANALOG Page
          4. 7.6.1.1.4 SERDES_XX Page Register Description
            1. 7.6.1.1.4.1  Register 20h (address = 20h) [reset = 0h], SERDES_XX Page
            2. 7.6.1.1.4.2  Register 21h (address = 21h) [reset = 0h], SERDES_XX Page
            3. 7.6.1.1.4.3  Register 22h (address = 22h) [reset = 0h], SERDES_XX Page
            4. 7.6.1.1.4.4  Register 23h (address = 23h) [reset = 0h], SERDES_XX Page
            5. 7.6.1.1.4.5  Register 25h (address = 25h) [reset = 0h], SERDES_XX Page
            6. 7.6.1.1.4.6  Register 26h (address = 26h) [reset = 0h], SERDES_XX Page
            7. 7.6.1.1.4.7  Register 28h (address = 28h) [reset = 0h], SERDES_XX Page
            8. 7.6.1.1.4.8  Register 2Dh (address = 2Dh) [reset = 0h], SERDES_XX Page
            9. 7.6.1.1.4.9  Register 36h (address = 36h) [reset = 0h], SERDES_XX Page
            10. 7.6.1.1.4.10 Register 41h (address = 41h) [reset = 0h], SERDES_XX Page
            11. 7.6.1.1.4.11 Register 42h (address = 42h) [reset = 0h], SERDES_XX Page
          5. 7.6.1.1.5 CHX Page Register Description
            1. 7.6.1.1.5.1 Register 26h (address = 26h) [reset = 0h], CHX Page
            2. 7.6.1.1.5.2 Register 27h (address = 27h) [reset = 0h], CHX Page
            3. 7.6.1.1.5.3 Register 2Dh (address = 2Dh) [reset = 0h], CHX Page
            4. 7.6.1.1.5.4 Register 78h (address = 78h) [reset = 0h], CHX Page
            5. 7.6.1.1.5.5 Register 7Ah (address = 7Ah) [reset = 0h], CHX Page
            6. 7.6.1.1.5.6 Register 7Bh (address = 7Bh) [reset = 0h], CHX Page
            7. 7.6.1.1.5.7 Register 7Eh (address = 7Eh) [reset = 3h], CHX Page
          6. 7.6.1.1.6 ADCXX Page Register Description
            1. 7.6.1.1.6.1 Register 07h (address = 07h) [reset = FFh], ADCXX Page
            2. 7.6.1.1.6.2 Register 08h (address = 08h) [reset = 0h], ADCXX Page
            3. 7.6.1.1.6.3 Register D5h (address = D5h) [reset = 0h], ADCXX Page
            4. 7.6.1.1.6.4 Register 2Ah (address = 2Ah) [reset = 0h], ADCXX Page
            5. 7.6.1.1.6.5 Register CFh (address = CFh) [reset = 0h], ADCXX Page
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
      3. 8.1.3 Frequency Planning
      4. 8.1.4 SNR and Clock Jitter
      5. 8.1.5 ADC Test Pattern
        1. 8.1.5.1 ADC Section
        2. 8.1.5.2 Transport Layer Pattern
        3. 8.1.5.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage AVDD19 –0.3 2.1 V
AVDD –0.3 1.4
DVDD –0.3 1.4
Voltage between AGND and DGND –0.3 0.3 V
Voltage applied to input pins INAP, INBP, INAM, INBM, INCP, INDP, INCM, INDM –0.3 2.1 V
CLKINP, CLKINM –0.3 AVDD + 0.3
SYSREFP, SYSREFM –0.3 1.9
SCLK, SEN, SDIN, RESET, SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM, PDN, TRIGAB, TRIGCD –0.2 AVDD19 + 0.3
Storage temperature, Tstg –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage range AVDD19 1.8 1.9 2 V
AVDD 1.1 1.15 1.2
DVDD 1.1 1.15 1.2
Analog inputs Differential input voltage range 1.1 VPP
Input common-mode voltage (VCM) 1.3 V
Clock inputs Input clock frequency, device clock frequency 400 1000 MHz
Input clock amplitude differential
(VCLKP – VCLKM)
Sine wave, ac-coupled 1.5 VPP
LVPECL, ac-coupled 1.6
LVDS, ac-coupled 0.7
Input device clock duty cycle, default after reset 45% 50% 55%
Temperature Operating free-air, TA –40 100(2) ºC
Operating junction, TJ 105(1)
Specified maximum, measured at the device footprint thermal pad on the printed circuit board, TP-MAX 104.5(1)
Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.
The recommended maximum temperature at the PCB footprint thermal pad assumes the junction-to-package bottom thermal resistance, RθJC(bot) = 0.2°C/W, the thermal resistance of the device thermal pad connection to the PCB footprint is negligible, and the device power consumption is 2.5 W.
Assumes system thermal design meets the TJ specification.

Thermal Information

THERMAL METRIC(1) ADS54J64 UNIT
RMP (VQFNP)
72 PINS
RθJA Junction-to-ambient thermal resistance (1) 22.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance (2) 5.1 °C/W
RθJB Junction-to-board thermal resistance (2) 2.4 °C/W
ψJT Junction-to-top characterization parameter (3) 0.1 °C/W
ψJB Junction-to-board characterization parameter (4) 2.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance (5) 0.2 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

Electrical Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency = 1 GHz, 50% clock duty cycle, output sample rate = 500 MSPS, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
ADC sampling rate 1 GSPS
Resolution 14 Bits
POWER SUPPLY
AVDD19 1.9-V analog supply 1.85 1.9 1.95 V
AVDD 1.15-V analog supply 1.1 1.15 1.2 V
DVDD 1.15-V digital supply 1.1 1.15 1.2 V
IAVDD19 1.9-V analog supply current 100-MHz, full-scale input on all four channels 618 mA
IAVDD 1.15-V analog supply current 100-MHz, full-scale input on all four channels 415 mA
IDVDD 1.15-V digital supply current DDC bypass mode (mode 8), 100-MHz, full-scale input on all four channels 629 mA
Mode 3, 100-MHz, full-scale input on all four channels 730
Mode 0 and 2, 100-MHz, full-scale input on all four channels 674
Mode 1, 4, 6, and 7, 100-MHz, full-scale input on all four channels 703
PDIS Total power dissipation DDC bypass mode (mode 8), 100-MHz, full-scale input on all four channels 2.37 W
Mode 3, 100-MHz, full-scale input on all four channels 2.49
Mode 0 and 2, 100-MHz, full-scale input on all four channels 2.42
Mode 1, 4, 6, and 7, 100-MHz, full-scale input on all four channels 2.46
Global power-down power dissipation Full-scale input on all four channels 120 mW
ANALOG INPUTS
Differential input full-scale voltage 1.1 VPP
Input common-mode voltage 1.3 V
Differential input resistance At fIN = dc 4
Differential input capacitance 2.5 pF
Analog input bandwidth (3 dB) 1000 MHz
ISOLATION
Crosstalk(1) isolation between near channels
(channels A and B are near to each other, channels C and D are near to each other)
fIN = 10 MHz 75 dBFS
fIN = 100 MHz 75
fIN = 170 MHz 74
fIN = 270 MHz 72
fIN = 370 MHz 71
fIN = 470 MHz 70
Crosstalk(1) isolation between far channels
(channels A and B are far from channels C and D)
fIN = 10 MHz 110 dBFS
fIN = 100 MHz 110
fIN = 170 MHz 110
fIN = 270 MHz 110
fIN = 370 MHz 110
fIN = 470 MHz 110
CLOCK INPUT
Internal clock biasing CLKINP and CLKINM pins are connected to the internal biasing voltage through a 5-kΩ resistor 0.7 V
Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.

AC Performance

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency = 1 GHz, 50% clock duty cycle, output sample rate = 500 MSPS, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
DDC BYPASS MODE DECIMATE-BY-4
(DDC Mode 2)
SNR Signal-to-noise ratio fIN = 10 MHz, AIN = –1 dBFS 69.9 72.2 dBFS
fIN = 70 MHz, AIN = –1 dBFS 69.6 71.8
fIN = 190 MHz, AIN = –1 dBFS 69.2 71.8
fIN = 190 MHz, AIN = –3 dBFS 66.5 69.6 71
fIN = 300 MHz, AIN = –3 dBFS 69.3 71.7
fIN = 370 MHz, AIN = –3 dBFS 68.7 71.3
fIN = 470 MHz, AIN = –3 dBFS 68.4 69.8
NSD Noise spectral density fIN = 10 MHz, AIN = –1 dBFS –153.9 –153.2 dBFS/Hz
fIN = 70 MHz, AIN = –1 dBFS –153.6 –152.8
fIN = 190 MHz, AIN = –1 dBFS –153.2 –152.7
fIN = 190 MHz, AIN = –3 dBFS –150.5 –153.6 –153.2
fIN = 300 MHz, AIN = –3 dBFS –152.8 –152.7
fIN = 370 MHz, AIN = –3 dBFS –152.5 –152.2
fIN = 470 MHz, AIN = –3 dBFS –151.5 –151
SFDR(1) Spurious-free dynamic range fIN = 10 MHz, AIN = –1 dBFS 83 83 dBc
fIN = 70 MHz, AIN = –1 dBFS 81 100
fIN = 190 MHz, AIN = –1 dBFS 87 100
fIN = 190 MHz, AIN = –3 dBFS 78 88 98
fIN = 300 MHz, AIN = –3 dBFS 79 98
fIN = 370 MHz, AIN = –3 dBFS,
input clock frequency = 983.04 MHz
82 70
fIN = 470 MHz, AIN = –3 dBFS 78 76
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz, AIN = –1 dBFS 68.5 70.6 dBFS
fIN = 70 MHz, AIN = –1 dBFS 68.5 70.6
fIN = 190 MHz, AIN = –1 dBFS 68.2 72.2
fIN = 190 MHz, AIN = –3 dBFS 68.5 73
fIN = 300 MHz, AIN = –3 dBFS 68.9 72.3
fIN = 370 MHz, AIN = –3 dBFS 68 68.2
fIN = 470 MHz, AIN = –3 dBFS 68 69
HD2(1) Second-order harmonic distortion fIN = 10 MHz, AIN = –1 dBFS –83 –90 dBc
fIN = 70 MHz, AIN = –1 dBFS –82 –100
fIN = 190 MHz, AIN = –1 dBFS –85 –98
fIN = 190 MHz, AIN = –3 dBFS –78 –86 –100
fIN = 300 MHz, AIN = –3 dBFS –82 –100
fIN = 370 MHz, AIN = –3 dBFS
input clock frequency = 983.04 MHz
–82 –69
fIN = 470 MHz, AIN = –3 dBFS –100 –94
HD3(1) Third-order harmonic distortion fIN = 10 MHz, AIN = –1 dBFS –83 –85 dBc
fIN = 70 MHz, AIN = –1 dBFS –81 –100
fIN = 190 MHz, AIN = –1 dBFS –92 –100
fIN = 190 MHz, AIN = –3 dBFS –78 –92 –100
fIN = 300 MHz, AIN = –3 dBFS –90 –100
fIN = 370 MHz, AIN = –3 dBFS –90 –100
fIN = 470 MHz, AIN = –3 dBFS –80 –79
Non
HD2, HD3
Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz, AIN = –1 dBFS 95 –100 dBFS
fIN = 70 MHz, AIN = –1 dBFS 95 –92
fIN = 190 MHz, AIN = –1 dBFS 95 –100
fIN = 190 MHz, AIN = –3 dBFS 87 95 –98
fIN = 300 MHz, AIN = –3 dBFS 95 –100
fIN = 370 MHz, AIN = –3 dBFS 95 –100
fIN = 470 MHz, AIN = –3 dBFS 93 –100
THD(1) Total harmonic distortion fIN = 10 MHz, AIN = –1 dBFS –81 –83 dBc
fIN = 70 MHz, AIN = –1 dBFS –79 –100
fIN = 190 MHz, AIN = –1 dBFS –83 –100
fIN = 190 MHz, AIN = –3 dBFS –85 –100
fIN = 300 MHz, AIN = –3 dBFS –81 –100
fIN = 370 MHz, AIN = –3 dBFS –76 –68
fIN = 470 MHz, AIN = –3 dBFS –82 –80
IMD3 Two-tone, third-order intermodulation distortion f1 = 185 MHz, f2 = 190 MHz,
AIN = –10 dBFS
–90 –87 dBFS
f1 = 365 MHz, f2 = 370 MHz,
AIN = –10 dBFS
–90 –94
f1 = 465 MHz, f2 = 470 MHz,
AIN = –10 dBFS
–85 –85
Harmonic distortion performance can be significantly improved by using the frequency planning explained in the Frequency Planning section.

Digital Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency = 1 GHz, 50% clock duty cycle, output sample rate = 500 MSPS, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, TRIGAB, TRIGCD)(1)
VIH High-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.8 V
VIL Low-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.4 V
IIH High-level input current SEN 0 µA
RESET, SCLK, SDIN, PDN, TRIGAB, TRIGCD 50
IIL Low-level input current SEN 50 µA
RESET, SCLK, SDIN, PDN, TRIGAB, TRIGCD 0
Input capacitance 4 pF
DIGITAL INPUTS
VD Differential input voltage SYSREFP, SYSREFM 0.35 0.45 0.55 V
SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP 0.35 0.45 0.8
V(CM_DIG) Common-mode voltage for SYSREF SYSREFP, SYSREFM 0.9 1.2 1.4 V
SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP 0.9 1.2 1.4
DIGITAL OUTPUTS (SDOUT, TRDYAB, TRDYCD)
VOH High-level output voltage 100-µA current AVDD19 – 0.2 V
VOL Low-level output voltage 100-µA current 0.2 V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2)
VOD Output differential voltage With default swing setting 700 mVPP
VOC Output common-mode voltage 450 mV
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
zos Single-ended output impedance 50 Ω
Output capacitance Output capacitance inside the device,
from either output to ground
2 pF
The RESET, SCLK, SDIN, and PDN pins have a 10-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 10-kΩ (typical) pullup resistor to DVDD.
50-Ω, single-ended external termination to DVDD.

Timing Characteristics

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency = 1 GHz, 50% clock duty cycle, output sample rate = 500 MSPS, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
MIN TYP MAX UNITS
SAMPLE TIMING CHARACTERISTICS
Aperture delay 0.55 0.92 ns
Aperture delay matching between two channels on the same device ±100 ps
Aperture delay matching between two devices at the same temperature and supply voltage ±100 ps
Aperture jitter 100 fS rms
Wake-up time Global power-down 10 ms
Pin power-down (fast power-down) 5 µs
Data latency: ADC sample to digital output DDC bypass mode 116 Input clock cycles
DDC mode 0 204
tSU_SYSREF Setup time for SYSREF, referenced to input clock rising edge 350 900 ps
tH_SYSREF Hold time for SYSREF, referenced to input clock rising edge 100 ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval 100 ps
Serial output data rate 10 Gbps
Total jitter for BER of 1E-15 and lane rate = 10 Gbps 24 ps
Random jitter for BER of 1E-15 and lane rate = 10 Gbps 0.95 ps rms
Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 8.8 ps, pk-pk
tR, tF Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps 35 ps
ADS54J64 elect_char_clk_sbas807.gif Figure 1. Latency Timing Diagram in DDC Bypass Mode

Typical Characteristics: DDC Bypass Mode

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency = 1 GSPS, 50% clock duty cycle, output sample rate = 500 MSPS, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
ADS54J64 D001_SBAS807.gif
fIN = 100 MHz, AIN = –1 dBFS, SNR = 69.57 dBFS,
SFDR = 85.23 dBc, SFDR = 102.09 dBc (non 23)
Figure 2. FFT for 100-MHz Input Signal
ADS54J64 D003_SBAS807.gif
fIN = 190 MHz, AIN = –3 dBFS, SNR = 69.60 dBFS,
SFDR = 88.45 dBc, SFDR = 99.78 dBc (non 23)
Figure 4. FFT for 190-MHz Input Signal
ADS54J64 D005_SBAS807.gif
fIN = 190 MHz, AIN = –20 dBFS, SNR = 70.23 dBFS,
SFDR = 81.71 dBc, SFDR = 81.71 dBc (non 23)
Figure 6. FFT for 190-MHz Input Signal
ADS54J64 D007_SBAS807.gif
fIN = 270 MHz, AIN = –3 dBFS, SNR = 69.27 dBFS,
SFDR = 82.98 dBc, SFDR = 95.4 dBc (non 23)
Figure 8. FFT for 270-MHz Input Signal
ADS54J64 D009_SBAS807.gif
fIN = 470 MHz, AIN = –3 dBFS, SNR = 68.21 dBFS,
SFDR = 79.85 dBc, SFDR = 99.12 dBc (non 23)
Figure 10. FFT for 470-MHz Input Signal
ADS54J64 D011_SBAS807.gif
fIN1 = 160 MHz, fIN2 = 170 MHz, IMD = 103.44 dBFS,
each tone at –10 dBFS
Figure 12. FFT for Two-Tone Input Signal
ADS54J64 D013_SBAS807.gif
fIN1 = 340 MHz, fIN2 = 350 MHz, IMD = 95.08 dBFS,
each tone at –10 dBFS
Figure 14. FFT for Two-Tone Input Signal
ADS54J64 D015_SBAS807.gif
Figure 16. HD3 vs Input Frequency
ADS54J64 D017_SBAS807.gif
Figure 18. SNR vs Input Frequency and Temperature
ADS54J64 D019_SBAS807.gif
Figure 20. HD2 vs Input Frequency and Temperature
ADS54J64 D021_SBAS807.gif
Figure 22. HD3 vs Input Frequency and AVDD19 Supply
ADS54J64 D023_SBAS807.gif
Figure 24. HD3 vs Input Frequency and AVDD Supply
ADS54J64 D025_SBAS807.gif
Figure 26. HD3 vs Input Frequency and DVDD Supply
ADS54J64 D027_SBAS807.gif
fIN = 370 MHz
Figure 28. Performance vs Input Signal Amplitude
ADS54J64 D029_SBAS841.gif
fIN1 = 340 MHz, fIN2 = 350 MHz
Figure 30. IMD vs Input Amplitude
ADS54J64 D031_SBAS807.gif
fIN = 190 MHz, AIN = –1 dBFS, fNoise = 5 MHz, ANoise = 50 mVPP
Figure 32. PSRR vs Power-Supply Noise Frequency
ADS54J64 D033_SBAS807.gif
fIN = 190 MHz, AIN = –1 dBFS, fNoise = 5 MHz, ANoise = 50 mVPP
Figure 34. CMRR vs Common-Mode Noise Frequency
ADS54J64 D002_SBAS807.gif
fIN = 190 MHz, AIN = –1 dBFS, SNR = 69.23 dBFS,
SFDR = 86.83 dBc, SFDR = 91.23 dBc (non 23)
Figure 3. FFT for 190-MHz Input Signal
ADS54J64 D004_SBAS807.gif
fIN = 190 MHz, AIN = –10 dBFS, SNR = 70.05 dBFS,
SFDR = 93.27 dBc, SFDR = 97.26 dBc (non 23)
Figure 5. FFT for 190-MHz Input Signal
ADS54J64 D006_SBAS807.gif
fIN = 230 MHz, AIN = –1 dBFS, SNR = 69.17 dBFS,
SFDR = 85.29 dBc, SFDR = 89.30 dBc (non 23)
Figure 7. FFT for 230-MHz Input Signal
ADS54J64 D008_SBAS807.gif
fIN = 370 MHz, AIN = –3 dBFS, SNR = 68.36 dBFS,
SFDR = 81.37 dBc, SFDR = 97.28 dBc (non 23)
Figure 9. FFT for 370-MHz Input Signal
ADS54J64 D010_SBAS807.gif
fIN1 = 160 MHz, fIN2 = 170 MHz, IMD = 102.68 dBFS,
each tone at –7 dBFS
Figure 11. FFT for Two-Tone Input Signal
ADS54J64 D012_SBAS807.gif
fIN1 = 340 MHz, fIN2 = 350 MHz, IMD = 84.34 dBFS,
each tone at –7 dBFS
Figure 13. FFT for Two-Tone Input Signal
ADS54J64 D014_SBAS807.gif
Figure 15. SNR vs Input Frequency
ADS54J64 D016_SBAS807.gif
Figure 17. HD2 vs Input Frequency
ADS54J64 D018_SBAS807.gif
Figure 19. HD3 vs Input Frequency and Temperature
ADS54J64 D020_SBAS807.gif
Figure 21. SNR vs Input Frequency and AVDD19 Supply
ADS54J64 D022_SBAS807.gif
Figure 23. SNR vs Input Frequency and AVDD Supply
ADS54J64 D024_SBAS807.gif
Figure 25. SNR vs Input Frequency and DVDD Supply
ADS54J64 D026_SBAS807.gif
fIN = 190 MHz
Figure 27. Performance vs Input Signal Amplitude
ADS54J64 D028_SBAS807.gif
fIN1 = 160 MHz, fIN2 = 170 MHz
Figure 29. IMD vs Input Amplitude
ADS54J64 D030_SBAS807.gif
fIN = 190 MHz, AIN = –1 dBFS, fNoise = 5 MHz,
ANoise = 50 mVPP, SFDR = 73.5 dBFS
Figure 31. Power-Supply Rejection Ratio FFT
for 50-mV Noise on AVDD Supply
ADS54J64 D032_SBAS807.gif
fIN = 190 MHz, AIN = –1 dBFS, fNoise = 5 MHz,
ANoise = 50 mVPP, SFDR = 63.12 dBFS
Figure 33. Common-Mode Rejection Ratio FFT
ADS54J64 D034_SBAS807.gif
Figure 35. Power Consumption vs Sampling Speed

Typical Characteristics: Mode 2

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency = 1 GSPS, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
ADS54J64 D035_SBAS807.gif
fIN = 150 MHz, AIN= –1 dBFS, SNR = 72.85 dBFS,
SFDR = 84.41 dBc, SFDR = 100.99 dBc (non 23)
Figure 36. FFT for 150-MHz Input Signal
ADS54J64 D037_SBAS807.gif
fIN = 300 MHz, AIN= –3 dBFS, SNR = 72.3 dBFS,
SFDR = 100.31 dBc, SFDR = 100.75 dBc (non 23)
Figure 38. FFT for 300-MHz Input Signal
ADS54J64 D036_SBAS807.gif
fIN = 190 MHz, AIN= –1 dBFS, SNR = 72.37 dBFS,
SFDR = 99.95 dBc, SFDR = 100.76 dBc (non 23)
Figure 37. FFT for 190-MHz Input Signal
ADS54J64 D038_SBAS807.gif
fIN = 350 MHz, AIN= –3 dBFS, SNR = 72.02 dBFS,
SFDR = 79.23 dBc, SFDR = 96.42 dBc (non 23)
Figure 39. FFT for 350-MHz Input Signal

Typical Characteristics: Mode 0

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency = 1 GSPS, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
ADS54J64 D039_SBAS807.gif
fIN = 100 MHz, AIN= –1 dBFS, SNR = 70.16 dBFS,
SFDR = 84.95 dBc, SFDR = 95.41 dBc (non 23)
Figure 40. FFT for 100-MHz Input Signal
ADS54J64 D041_SBAS807.gif
fIN = 220 MHz, AIN= –1 dBFS, SNR = 69.27 dBFS,
SFDR = 87.66 dBc, SFDR = 91.04 dBc (non 23)
Figure 42. FFT for 220-MHz Input Signal
ADS54J64 D040_SBAS807.gif
fIN = 170 MHz, AIN= –1 dBFS, SNR = 69.35 dBFS,
SFDR = 86.46 dBc, SFDR = 89.27 dBc (non 23)
Figure 41. FFT for 170-MHz Input Signal

Typical Characteristics: Dual ADC Mode

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency = 1 GSPS, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
ADS54J64 D046_SBAS841.gif
fIN = 230 MHz, AIN= –1 dBFS, SNR = 68.11 dBFS,
SFDR = 77.01 dBc, interleaving spur = –42.85 dBFS
Figure 43. FFT for 230-MHz Input Signal
ADS54J64 D048_SBAS841.gif
Figure 45. Interleaving Spur vs Input Frequency
ADS54J64 D047_SBAS841.gif
fIN = 470 MHz, AIN= –1 dBFS, SNR = 66.56 dBFS,
SFDR = 72.32 dBc, interleaving spur = –36.96 dBFS
Figure 44. FFT for 470-MHz Input Signal