SBAS844 May   2017 ADC32RF42

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Family Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Performance Characteristics
    7. 7.7 Digital Requirements
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Input Clock Diagram
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
        1. 9.3.1.1 Input Clamp Circuit
      2. 9.3.2  Clock Input
      3. 9.3.3  SYSREF Input
        1. 9.3.3.1 Using SYSREF
        2. 9.3.3.2 Frequency of the SYSREF Signal
      4. 9.3.4  DDC Block
        1. 9.3.4.1 Operating Mode: Receiver
        2. 9.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver
        3. 9.3.4.3 Decimation Filters
          1. 9.3.4.3.1 Divide-by-4
          2. 9.3.4.3.2 Divide-by-6
          3. 9.3.4.3.3 Divide-by-8
          4. 9.3.4.3.4 Divide-by-9
          5. 9.3.4.3.5 Divide-by-10
          6. 9.3.4.3.6 Divide-by-12
          7. 9.3.4.3.7 Divide-by-16
        4. 9.3.4.4 Digital Multiplexer (MUX)
        5. 9.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers
      5. 9.3.5  NCO Switching
      6. 9.3.6  SerDes Transmitter Interface
      7. 9.3.7  Eye Diagrams
      8. 9.3.8  Alarm Outputs: Power Detectors for AGC Support
        1. 9.3.8.1 Absolute Peak Power Detector
        2. 9.3.8.2 Crossing Detector
        3. 9.3.8.3 RMS Power Detector
        4. 9.3.8.4 GPIO AGC MUX
      9. 9.3.9  Power-Down Mode
      10. 9.3.10 ADC Test Pattern
        1. 9.3.10.1 Digital Block
        2. 9.3.10.2 Transport Layer
        3. 9.3.10.3 Link Layer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Configuration
      2. 9.4.2 JESD204B Interface
        1. 9.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.4.2.2 JESD204B Frame Assembly
        3. 9.4.2.3 JESD204B Frame Assembly in Bypass Mode
        4. 9.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
        5. 9.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        6. 9.4.2.6 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        7. 9.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
        8. 9.4.2.8 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
      3. 9.4.3 Serial Interface
        1. 9.4.3.1 Serial Register Write: Analog Bank
        2. 9.4.3.2 Serial Register Readout: Analog Bank
        3. 9.4.3.3 Serial Register Write: Digital Bank
        4. 9.4.3.4 Serial Register Readout: Digital Bank
        5. 9.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
    5. 9.5 Register Maps
      1. 9.5.1  Example Register Writes
      2. 9.5.2  Register Descriptions
        1. 9.5.2.1 General Registers
          1. 9.5.2.1.1 Register 000h (address = 000h), General Registers
          2. 9.5.2.1.2 Register 002h (address = 002h), General Registers
          3. 9.5.2.1.3 Register 003h (address = 003h), General Registers
          4. 9.5.2.1.4 Register 004h (address = 004h), General Registers
          5. 9.5.2.1.5 Register 010h (address = 010h), General Registers
          6. 9.5.2.1.6 Register 011h (address = 011h), General Registers
          7. 9.5.2.1.7 Register 012h (address = 012h), General Registers
      3. 9.5.3  Master Page (M = 0)
        1. 9.5.3.1 Register 020h (address = 020h), Master Page
        2. 9.5.3.2 Register 032h (address = 032h), Master Page
        3. 9.5.3.3 Register 039h (address = 039h), Master Page
        4. 9.5.3.4 Register 03Ch (address = 03Ch), Master Page
        5. 9.5.3.5 Register 05Ah (address = 05Ah), Master Page
        6. 9.5.3.6 Register 03Dh (address = 3Dh), Master Page
        7. 9.5.3.7 Register 057h (address = 057h), Master Page
        8. 9.5.3.8 Register 058h (address = 058h), Master Page
      4. 9.5.4  ADC Page (FFh, M = 0)
        1. 9.5.4.1 Register 03Fh (address = 03Fh), ADC Page
        2. 9.5.4.2 Register 042h (address = 042h), ADC Page
      5. 9.5.5  Offset Corr Page Channel A (610000h, M = 1)
        1. 9.5.5.1 Register 068h (address = 068h), Offset Corr Page Channel A
      6. 9.5.6  Offset Corr Page Channel B (610100h, M = 1)
        1. 9.5.6.1 Register 068h (address = 068h), Offset Corr Page Channel B
      7. 9.5.7  Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
        1. 9.5.7.1 Register 0A6h (address = 0A6h), Digital Gain Page
      8. 9.5.8  Main Digital Page Channel A (680000h, M = 1)
        1. 9.5.8.1 Register 000h (address = 000h), Main Digital Page Channel A
        2. 9.5.8.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A
      9. 9.5.9  Main Digital Page Channel B (680100h, M = 1)
        1. 9.5.9.1 Register 0A2h (address = 0A2h), Main Digital Page Channel B
      10. 9.5.10 JESD Digital Page (690000h, M = 1)
        1. 9.5.10.1  Register 001h (address = 001h), JESD Digital Page
        2. 9.5.10.2  Register 002h (address = 002h ), JESD Digital Page
        3. 9.5.10.3  Register 003h (address = 003h), JESD Digital Page
        4. 9.5.10.4  Register 004h (address = 004h), JESD Digital Page
        5. 9.5.10.5  Register 006h (address = 006h), JESD Digital Page
        6. 9.5.10.6  Register 007h (address = 007h), JESD Digital Page
        7. 9.5.10.7  Register 016h (address = 016h), JESD Digital Page
        8. 9.5.10.8  Register 017h (address = 017h), JESD Digital Page
        9. 9.5.10.9  Register 032h-035h (address = 032h-035h), JESD Digital Page
        10. 9.5.10.10 Register 036h (address = 036h), JESD Digital Page
        11. 9.5.10.11 Register 037h (address = 037h), JESD Digital Page
        12. 9.5.10.12 Register 03Ch (address = 03Ch), JESD Digital Page
        13. 9.5.10.13 Register 03Eh (address = 03Eh), JESD Digital Page
      11. 9.5.11 Special Page Channel A
        1. 9.5.11.1 Register 019h (address = 019h), Special Page Channel A
      12. 9.5.12 Special Page Channel B
        1. 9.5.12.1 Register 019h (address = 019h), Special Page Channel B
      13. 9.5.13 Decimation Filter Page
        1. 9.5.13.1  Register 000h (address = 000h), Decimation Filter Page
        2. 9.5.13.2  Register 001h (address = 001h), Decimation Filter Page
        3. 9.5.13.3  Register 002h (address = 2h), Decimation Filter Page
        4. 9.5.13.4  Register 005h (address = 005h), Decimation Filter Page
        5. 9.5.13.5  Register 006h (address = 006h), Decimation Filter Page
        6. 9.5.13.6  Register 007h (address = 007h), Decimation Filter Page
        7. 9.5.13.7  Register 008h (address = 008h), Decimation Filter Page
        8. 9.5.13.8  Register 009h (address = 009h), Decimation Filter Page
        9. 9.5.13.9  Register 00Ah (address = 00Ah), Decimation Filter Page
        10. 9.5.13.10 Register 00Bh (address = 00Bh), Decimation Filter Page
        11. 9.5.13.11 Register 00Ch (address = 00Ch), Decimation Filter Page
        12. 9.5.13.12 Register 00Dh (address = 00Dh), Decimation Filter Page
        13. 9.5.13.13 Register 00Eh (address = 00Eh), Decimation Filter Page
        14. 9.5.13.14 Register 00Fh (address = 00Fh), Decimation Filter Page
        15. 9.5.13.15 Register 010h (address = 010h), Decimation Filter Page
        16. 9.5.13.16 Register 011h (address = 011h), Decimation Filter Page
        17. 9.5.13.17 Register 014h (address = 014h), Decimation Filter Page
        18. 9.5.13.18 Register 016h (address = 016h), Decimation Filter Page
        19. 9.5.13.19 Register 01Eh (address = 01Eh), Decimation Filter Page
        20. 9.5.13.20 Register 01Fh (address = 01Fh), Decimation Filter Page
        21. 9.5.13.21 Register 020h (address = 020h), Decimation Filter Page
        22. 9.5.13.22 Register 033h-036h (address = 033h-036h), Decimation Filter Page
        23. 9.5.13.23 Register 037h (address = 037h), Decimation Filter Page
        24. 9.5.13.24 Register 038h (address = 038h), Decimation Filter Page
        25. 9.5.13.25 Register 039h (address = 039h), Decimation Filter Page
        26. 9.5.13.26 Register 03Ah (address = 03Ah), Decimation Filter Page
      14. 9.5.14 Power Detector Page
        1. 9.5.14.1  Register 000h (address = 000h), Power Detector Page
        2. 9.5.14.2  Register 001h-002h (address = 001h-002h), Power Detector Page
        3. 9.5.14.3  Register 003h (address = 003h), Power Detector Page
        4. 9.5.14.4  Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
        5. 9.5.14.5  Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
        6. 9.5.14.6  Register 00Dh (address = 00Dh), Power Detector Page
        7. 9.5.14.7  Register 00Eh (address = 00Eh), Power Detector Page
        8. 9.5.14.8  Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power Detector Page
        9. 9.5.14.9  Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
        10. 9.5.14.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
        11. 9.5.14.11 Register 020h (address = 020h), Power Detector Page
        12. 9.5.14.12 Register 021h (address = 021h), Power Detector Page
        13. 9.5.14.13 Register 022h-025h (address = 022h-025h), Power Detector Page
        14. 9.5.14.14 Register 027h (address = 027h), Power Detector Page
        15. 9.5.14.15 Register 02Bh (address = 02Bh), Power Detector Page
        16. 9.5.14.16 Register 037h (address = 037h), Power Detector Page
        17. 9.5.14.17 Register 038h (address = 038h), Power Detector Page
        18. 9.5.14.18 Power Detector Page (Direct Addressing, 16-Bit Address, 5400h)
          1. 9.5.14.18.1 Register 032h-035h (address = 032h-035h), Power Detector Page
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-Up Sequence
      2. 10.1.2 Hardware Reset
      3. 10.1.3 SNR and Clock Jitter
        1. 10.1.3.1 External Clock Phase Noise Consideration
      4. 10.1.4 Power Consumption in Different Modes
      5. 10.1.5 Using DC Coupling in the ADC32RF42
        1. 10.1.5.1 Bypassing the Offset Corrector Block
          1. 10.1.5.1.1 Effect of Temperature
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Transformer-Coupled Circuits
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range AVDD19 –0.3 2.1 V
AVDD –0.3 1.4
DVDD –0.3 1.4
Voltage applied to input pins INAP, INAM and INBP, INBM –0.3 AVDD19 + 0.3 V
CLKINP, CLKINM –0.3 AVDD + 0.6
SYSREFP, SYSREFM, SYNCBP, SYNCBM –0.3 AVDD + 0.6
SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2, GPIO3, GPIO4 –0.2 AVDD19 + 0.2
Voltage applied to output pins –0.3 2.2 V
Temperature Operating free-air, TA –40 85 °C
Storage, Tstg –65 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage(2) AVDD19 1.8 1.9 2.0 V
AVDD 1.1 1.15 1.25
DVDD 1.1 1.15 1.2
Temperature Operating free-air, TA –40 85 °C
Operating junction, TJ 105(1) 125
Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
Always power up the DVDD supply (1.15 V) before the AVDD19 (1.9 V) supply. The AVDD (1.15 V) supply can come up in any order.

Thermal Information

THERMAL METRIC(1) ADC32RF42 UNIT
RMP (VQFN)
72 PINS
RθJA Junction-to-ambient thermal resistance 21.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 4.4 °C/W
RθJB Junction-to-board thermal resistance 2.0 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 2.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER CONSUMPTION(4) (Dual-Channel Operation, Both Channels A and B are Active; DDC Bypass Mode(3))
IAVDD19 1.9-V analog supply current 14-bit, bypass mode, fS = 1.5 GSPS 1150 1969 mA
IAVDD 1.15-V analog supply current 14-bit, bypass mode, fS = 1.5 GSPS 604 1079 mA
IDVDD 1.15-V digital supply current 14-bit, bypass mode, fS = 1.5 GSPS 1000 1846 mA
PD Power dissipation 14-bit, bypass mode, fS = 1.5 GSPS 4.03 6.95 W
Global power-down power dissipation 360 mW
ANALOG INPUTS
Resolution 14 Bits
Differential input full-scale 1.35 VPP
VIC Input common-mode voltage 1.2(5) V
RIN Input resistance Differential resistance at dc 65 Ω
CIN Input capacitance Differential capacitance at dc 2 pF
VCM common-mode voltage output 1.2 V
Analog input bandwidth
(–3-dB point)
ADC driven with 50-Ω source 3200 MHz
ISOLATION
Crosstalk isolation between channel A and channel B(1) fIN = 100 MHz 100 dBc
fIN = 900 MHz 99
fIN = 1800 MHz 95
fIN = 2700 MHz 86
fIN = 3500 MHz 85
CLOCK INPUT(2)
Input clock frequency 750 1500 MHz
Differential (peak-to-peak) input clock amplitude 0.5 1.5 2.5 VPP
Input clock duty cycle 45% 50% 55%
Internal clock biasing 1.0 V
Internal clock termination (differential) 100 Ω
Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.
See Figure 32.
Full-scale signal is applied to the analog inputs of all active channels.
See the Power Consumption in Different Modes section for more details.
When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best performance.

AC Performance Characteristics

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(2) NOM MAX UNIT
SNR Signal-to-noise ratio fIN = 100 MHz, AOUT = –2 dBFS 62.8 dBFS
fIN = 300 MHz, AOUT = –2 dBFS 62.6
fIN = 950 MHz, AOUT = –2 dBFS 61.1
fIN = 1200 MHz, AOUT = –2 dBFS 60.4
fIN = 1350 MHz, AOUT = –2 dBFS 60.0
fIN = 1850 MHz, AOUT = –2 dBFS 58.9
fIN = 2100 MHz, AOUT = –2 dBFS 57.9
NSD Noise spectral density averaged across the Nyquist zone fIN = 100 MHz, AOUT = –2 dBFS 151.6 dBFS/Hz
fIN = 300 MHz, AOUT = –2 dBFS 151.4
fIN = 950 MHz, AOUT = –2 dBFS 149.8
fIN = 1200 MHz, AOUT = –2 dBFS 149.1
fIN = 1350 MHz, AOUT = –2 dBFS 148.8
fIN = 1850 MHz, AOUT = –2 dBFS 147.6
fIN = 2100 MHz, AOUT = –2 dBFS 146.7
Small-signal SNR fIN = 950 MHz, AOUT = –40 dBFS 63.0 dBFS
NF(1) Input noise figure fIN = 950 MHz, AOUT = –40 dBFS 27.7 dB
SINAD Signal-to-noise and distortion ratio fIN = 100 MHz, AOUT = –2 dBFS 61.4 dBFS
fIN = 300 MHz, AOUT = –2 dBFS 61.0
fIN = 950 MHz, AOUT = –2 dBFS 60.9
fIN = 1200 MHz, AOUT = –2 dBFS 59.9
fIN = 1350 MHz, AOUT = –2 dBFS 59.2
fIN = 1850 MHz, AOUT = –2 dBFS 58.2
fIN = 2100 MHz, AOUT = –2 dBFS 55.8
ENOB Effective number of bits fIN = 100 MHz, AOUT = –2 dBFS 9.9 Bits
fIN = 300 MHz, AOUT = –2 dBFS 9.8
fIN = 950 MHz, AOUT = –2 dBFS 9.8
fIN = 1200 MHz, AOUT = –2 dBFS 9.6
fIN = 1350 MHz, AOUT = –2 dBFS 9.5
fIN = 1850 MHz, AOUT = –2 dBFS 9.4
fIN = 2100 MHz, AOUT = –2 dBFS 9.0
SFDR Spurious-free dynamic range fIN = 100 MHz, AOUT = –2 dBFS 67 dBc
fIN = 300 MHz, AOUT = –2 dBFS 64
fIN = 950 MHz, AOUT = –2 dBFS 70
fIN = 1200 MHz, AOUT = –2 dBFS 67
fIN = 1350 MHz, AOUT = –2 dBFS 66
fIN = 1850 MHz, AOUT = –2 dBFS 64
fIN = 2100 MHz, AOUT = –2 dBFS 58
HD2 Second-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 68 dBc
fIN = 300 MHz, AOUT = –2 dBFS 64
fIN = 950 MHz, AOUT = –2 dBFS 72
fIN = 1200 MHz, AOUT = –2 dBFS 70
fIN = 1350 MHz, AOUT = –2 dBFS 67
fIN = 1850 MHz, AOUT = –2 dBFS 64
fIN = 2100 MHz, AOUT = –2 dBFS 58
HD3 Third-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 67 dBc
fIN = 300 MHz, AOUT = –2 dBFS 71
fIN = 950 MHz, AOUT = –2 dBFS 70
fIN = 1200 MHz, AOUT = –2 dBFS 67
fIN = 1350 MHz, AOUT = –2 dBFS 70
fIN = 1850 MHz, AOUT = –2 dBFS 73
fIN = 2100 MHz, AOUT = –2 dBFS 66
HD4, HD5 Fourth- and fifth-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 89 dBc
fIN = 300 MHz, AOUT = –2 dBFS 84
fIN = 950 MHz, AOUT = –2 dBFS 85
fIN = 1200 MHz, AOUT = –2 dBFS 83
fIN = 1350 MHz, AOUT = –2 dBFS 85
fIN = 1850 MHz, AOUT = –2 dBFS 83
fIN = 2100 MHz, AOUT = –2 dBFS 82
IL spur Interleaving spur:
fS / 2 – fIN,
fIN = 100 MHz, AOUT = –2 dBFS 91 dBc
fIN = 300 MHz, AOUT = –2 dBFS 87
fIN = 950 MHz, AOUT = –2 dBFS 83
fIN = 1200 MHz, AOUT = –2 dBFS 82
fIN = 1350 MHz, AOUT = –2 dBFS 82
fIN = 1850 MHz, AOUT = –2 dBFS 82
fIN = 2100 MHz, AOUT = –2 dBFS 80
HD2 IL Interleaving spur for HD2:
fS / 2 – HD2
fIN = 100 MHz, AOUT = –2 dBFS 86 dBc
fIN = 300 MHz, AOUT = –2 dBFS 87
fIN = 950 MHz, AOUT = –2 dBFS 83
fIN = 1200 MHz, AOUT = –2 dBFS 80
fIN = 1350 MHz, AOUT = –2 dBFS 79
fIN = 1850 MHz, AOUT = –2 dBFS 79
fIN = 2100 MHz, AOUT = –2 dBFS 80
Worst spur Spurious-free dynamic range (excluding HD2, HD3, HD4, HD5, and interleaving spurs IL and HD2 IL) fIN = 100 MHz, AOUT = –2 dBFS 80 dBc
fIN = 300 MHz, AOUT = –2 dBFS 82
fIN = 950 MHz, AOUT = –2 dBFS 80
fIN = 1200 MHz, AOUT = –2 dBFS 82
fIN = 1350 MHz, AOUT = –2 dBFS 79
fIN = 1850 MHz, AOUT = –2 dBFS 80
fIN = 2100 MHz, AOUT = –2 dBFS 81
IMD3 Third-order intermodulation distortion fIN1 = 940 MHz, fIN2 = 960 MHz,
AOUT = –8 dBFS (each tone)
75 dBFS
The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω.
Minimum values are specified at AOUT = –3 dBFS.

Digital Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4)
VIH High-level input voltage 0.8 V
VIL Low-level input voltage 0.4 V
IIH High-level input current 50 µA
IIL Low-level input current –50 µA
Ci Input capacitance 4 pF
DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4)
VOH High-level output voltage AVDD19–0.1 AVDD19 V
VOL Low-level output voltage 0.1 V
DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing)
VID Differential input voltage 350 450 800 mVPP
VCM Input common-mode voltage 1.05 1.2 1.325 V
DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard)
|VOD| Output differential voltage 700 mVPP
|VOCM| Output common-mode voltage 450 mV
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
zos Single-ended output impedance 50 Ω
Co Output capacitance Output capacitance inside the device,
from either output to ground
2 pF

Timing Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
MIN NOM MAX UNIT
SAMPLE TIMING
Aperture delay 250 750 ps
Aperture delay matching between two channels on the same device ±15 ps
Aperture delay matching between two devices at the same
temperature and supply voltage
±150 ps
Aperture jitter, clock amplitude = 2 VPP 90 fS
Fast overrange latency, ADC sample to FOVR indication on GPIO pins 70 Input clock cycles
tPD Propagation delay time: logic gates and output buffer delay
(does not change with fS)
6 ns
SYSREF TIMING(1)
tSU_SYSREF SYSREF setup time: referenced to clock rising edge, 1.5 GSPS 140 70 ps
tH_SYSREF SYSREF hold time: referenced to clock rising edge, 1.5 GSPS 50 20 ps
Valid transition window sampling period: tSU_SYSREF – tH_SYSREF, 1.5 GSPS 476 ps
JESD OUTPUT INTERFACE TIMING
UI Unit interval: 12.5 Gbps 80 100 400 ps
Serial output data rate 2.5 10.0 12.5 Gbps
Rise, fall times: 1-pF, single-ended load capacitance to ground 60 ps
Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps 25 %UI
Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps 0.99 %UI, rms
Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps 9.1 %UI,
pk-pk
Common-mode voltage for the SYSREF input is kept at 1.2 V.
ADC32RF42 digital_inpt_outpts_sbas747.gif
VOCM is not the same as VICM. Similarly, VOD is not the same as VID.
Figure 1. Logic Levels for Digital Inputs and Outputs
ADC32RF42 tmg_rqrmnts_dgm_sbas747.gif Figure 2. SYSREF Timing Diagram

Typical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 65536 points FFT, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
ADC32RF42 D001_SBAS844.gif
SFDR = 73 dBc, SNR = 62.4 dBFS, SINAD = 62 dBFS,
THD = 71 dBc, HD2 = –75 dBFS, HD3 = –78 dBFS,
SFDR (non HD2, HD3) = 85 dBc, IL spur = 81 dBFS
Figure 3. FFT for 100-MHz Input Signal
ADC32RF42 D003_SBAS844.gif
SFDR = 65 dBc, SNR = 62.3 dBFS, SINAD = 61 dBFS,
THD = 64 dBc, HD2 = –67 dBFS, HD3 = –75 dBFS,
SFDR (non HD2, HD3) = 74 dBc, IL spur = 82 dBFS
Figure 5. FFT for 300-MHz Input Signal
ADC32RF42 D005_SBAS844.gif
SFDR = 72 dBc, SNR = 60.2 dBFS, SINAD = 60 dBFS,
THD = 71 dBc, HD2 = –74 dBFS, HD3 = –87 dBFS,
SFDR (non HD2, HD3) = 80 dBFS, IL spur = 80 dBFS
Figure 7. FFT for 1200-MHz Input Signal
ADC32RF42 D007_SBAS844.gif
SFDR = 59 dBc, SNR = 57.9 dBFS, SINAD = 56 dBFS,
HD2 = –61 dBFS, HD3 = –69 dBFS,
SFDR (non HD2, HD3) = 81 dBc, THD = 58 dBc,
IL spur = 83 dBFS
Figure 9. FFT for 2100-MHz Input Signal
ADC32RF42 D009_SBAS844.gif
fIN1 = 940 MHz, fIN2 = 960 MHz,
AOUT = –36 dBFS, IMD = 94 dBFS
Figure 11. FFT for Two-Tone Input Signal (–36 dBFS)
ADC32RF42 D011_SBAS844.gif
Figure 13. Spurious-Free Dynamic Range vs Input Frequency
ADC32RF42 D013_SBAS844.gif
Figure 15. Signal-to-Noise Ratio vs Input Frequency
ADC32RF42 D015_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 17. Spurious-Free Dynamic Range vs AVDD Supply and Temperature
ADC32RF42 D017_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 19. Spurious-Free Dynamic Range vs DVDD Supply and Temperature
ADC32RF42 D019_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 21. Spurious-Free Dynamic Range vs AVDD19 Supply and Temperature
ADC32RF42 D021_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 23. Performance vs Clock Amplitude
ADC32RF42 D023_SBAS844.gif
fIN = 1850 MHz, AIN = –2 dBFS, SNR = 63.8 dBFS,
SFDR (includes IL) = 78 dBc, fS = 1500 MSPS
Figure 25. FFT in 4x Decimation
ADC32RF42 D025_SBAS844.gif
fIN = 1850 MHz, AIN = –2 dBFS, SNR = 66 dBFS,
SFDR (includes IL) = 77 dBc, fS = 1500 MSPS
Figure 27. FFT in 8x Decimation
ADC32RF42 D027_SBAS844.gif
fIN = 1850 MHz, AIN = –2 dBFS, SNR = 65.9 dBFS,
SFDR (includes IL) = 74 dBc, fS = 1500 MSPS
Figure 29. FFT in 10x Decimation
ADC32RF42 D029_SBAS844.gif
fIN = 1850 MHz, AIN = –2 dBFS, SNR = 68.1 dBFS,
SFDR (includes IL) = 80.9 dBc, fS = 1500 MSPS
Figure 31. FFT in 16x Decimation
ADC32RF42 D002_SBAS844.gif
SFDR = 65 dBc, SNR = 62.3 dBFS, SINAD = 61 dBFS,
THD = 64 dBc, HD2 = –67 dBFS, HD3 = –73 dBFS,
SFDR (non HD2, HD3) = 89 dBc, IL spur = 81 dBFS
Figure 4. FFT for 185-MHz Input Signal
ADC32RF42 D004_SBAS844.gif
SFDR = 70 dBc, SNR = 60.8 dBFS, SINAD = 60 dBFS,
THD = 69 dBc, HD2 = –72 dBFS, HD3 = –78 dBFS,
SFDR (non HD2, HD3) = 81 dBc, IL spur = 82 dBFS
Figure 6. FFT for 950-MHz Input Signal
ADC32RF42 D006_SBAS844.gif
SFDR = 70 dBc, SNR = 58.7 dBFS, SINAD = 58 dBFS,
HD2 = –72 dBFS, HD3 = –75 dBFS,
SFDR (non HD2, HD3) = 79 dBc, THD = 68 dBc,
IL spur = 80 dBFS
Figure 8. FFT for 1850-MHz Input Signal
ADC32RF42 D008_SBAS844.gif
fIN1 = 940 MHz, fIN2 = 960 MHz,
AOUT = –8 dBFS, IMD = 75 dBFS
Figure 10. FFT for Two-Tone Input Signal (–8 dBFS)
ADC32RF42 D010_SBAS844.gif
Figure 12. Intermodulation Distortion vs Input Amplitude (940 MHz and 960 MHz)
ADC32RF42 D012_SBAS844.gif
Figure 14. IL Spur vs Input Frequency
ADC32RF42 D014_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 16. Signal-to-Noise Ratio vs AVDD Supply and Temperature
ADC32RF42 D016_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 18. Signal-to-Noise Ratio vs DVDD Supply and Temperature
ADC32RF42 D018_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 20. Signal-to-Noise Ratio vs AVDD19 Supply and Temperature
ADC32RF42 D020_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 22. Performance vs Amplitude
ADC32RF42 D022_SBAS844.gif
fIN = 950 MHz, AIN = –2 dBFS
Figure 24. Performance vs Clock Duty Cycle
ADC32RF42 D024_SBAS844.gif
fIN = 1850 MHz, AIN = –2 dBFS, SNR = 65 dBFS,
SFDR (includes IL) = 75 dBc, fS = 1500 MSPS
Figure 26. FFT in 6x Decimation
ADC32RF42 D026_SBAS844.gif
fIN = 1850 MHz, AIN = –2 dBFS, SNR = 65.8 dBFS,
SFDR (includes IL) = 74 dBc, fS = 1500 MSPS
Figure 28. FFT in 9x Decimation
ADC32RF42 D028_SBAS844.gif
fIN = 1850 MHz, AIN = –2 dBFS, SNR = 66.4 dBFS,
SFDR (includes IL) = 74.1 dBc, fS = 1500 MSPS
Figure 30. FFT in 12x Decimation