SBAS884A March 2020 – June 2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1
PRODUCTION DATA.
This register is the latched Interrupt status register for channel level diagnostic summary.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS_CHx_LTCH[7] | STS_CHx_LTCH[6] | STS_CHx_LTCH[5] | STS_CHx_LTCH[4] | STS_CHx_LTCH[3] | STS_CHx_LTCH[2] | STS_CHx_LTCH[1] | Reserved |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | STS_CHx_LTCH[7] | R | 0h | Status of CH1_LTCH (self-clearing bit).
0d = No faults occurred in channel 1 1d = Atleast a fault has occurred in channel 1 |
6 | STS_CHx_LTCH[6] | R | 0h | Status of CH2_LTCH (self-clearing bit).
0d = No faults occurred in channel 2 1d = Atleast a fault has occurred in channel 2 |
5 | STS_CHx_LTCH[5] | R | 0h | Status of CH3_LTCH (self-clearing bit).
0d = No faults occurred in channel 3 1d = Atleast a fault has occurred in channel 3 |
4 | STS_CHx_LTCH[4] | R | 0h | Status of CH4_LTCH (self-clearing bit).
0d = No faults occurred in channel 4 1d = Atleast a fault has occurred in channel 4 |
3 | STS_CHx_LTCH[3] | R | 0h | Status of CH5_LTCH (self-clearing bit). Applicable only for PCM6x60-Q1.
0d = No faults occurred in channel 5 1d = Atleast a fault has occurred in channel 5 |
2 | STS_CHx_LTCH[2] | R | 0h | Status of CH6_LTCH (self-clearing bit). Applicable only for PCM6x60-Q1.
0d = No faults occurred in channel 6 1d = Atleast a fault has occurred in channel 6 |
1 | STS_CHx_LTCH[1] | R | 0h | Status of short to VBAT_IN fault detected when VBAT_IN is less than MICBIAS (self-clearing bit).
0d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has not occurred in any channel 1d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has occurred in atleast one channel |
0 | Reserved | R | 0h | Reserved |