SBAS884A March 2020 – June 2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1
PRODUCTION DATA.
This register is the digital signal processor (DSP) configuration register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DVOL_GANG | BIQUAD_CFG[1:0] | DISABLE_SOFT_STEP | AGC_SEL | Reserved | Reserved | ||
RW-0h | RW-2h | RW-0h | RW-1h | RW-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DVOL_GANG | RW | 0h | DVOL control ganged across channels.
0d = Each channel has its own DVOL CTRL settings as programmed in the CHx_DVOL bits 1d = All active channels must use the channel 1 DVOL setting (CH1_DVOL) irrespective of whether channel 1 is turned on or not |
6-5 | BIQUAD_CFG[1:0] | RW | 2h | Number of biquads per channel configuration.
0d = No biquads per channel; biquads are all disabled 1d = 1 biquad per channel 2d = 2 biquads per channel 3d = 3 biquads per channel |
4 | DISABLE_SOFT_STEP | RW | 0h | Soft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled 1d = Soft-stepping disabled |
3 | AGC_SEL | RW | 1h | AGC master enable setting.
0d = Reserved; Write always 1 to this register bit 1d = AGC selected as configured for each channel using CHx_CFG0 register |
2 | Reserved | RW | 0h | Reserved |
1-0 | Reserved | R | 0h | Reserved |