SBASAF6A October   2021  – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3 ADC Core
        1. 6.3.3.1 ADC Core Calibration
        2. 6.3.3.2 ADC Theory of Operation
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Over-range Detection
        5. 6.3.3.5 Code Error Rate (CER)
        6. 6.3.3.6 Temperature Monitoring Diode
        7. 6.3.3.7 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        5. 6.3.4.5 JESD204C Interface
          1. 6.3.4.5.1  Transport Layer
          2. 6.3.4.5.2  Scrambler
          3. 6.3.4.5.3  Link Layer
          4. 6.3.4.5.4  8B/10B Link Layer
            1. 6.3.4.5.4.1 Data Encoding (8B/10B)
            2. 6.3.4.5.4.2 Multiframes and the Local Multiframe Clock (LMFC)
            3. 6.3.4.5.4.3 Code Group Synchronization (CGS)
            4. 6.3.4.5.4.4 Initial Lane Alignment Sequence (ILAS)
            5. 6.3.4.5.4.5 Frame and Multiframe Monitoring
          5. 6.3.4.5.5  64B/66B Link Layer
            1. 6.3.4.5.5.1 64B/66B Encoding
            2. 6.3.4.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. 6.3.4.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. 6.3.4.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
                2. 6.3.4.5.5.2.1.2 Forward Error Correction (FEC) Mode
            3. 6.3.4.5.5.3 Initial Lane Alignment
            4. 6.3.4.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
          6. 6.3.4.5.6  Physical Layer
            1. 6.3.4.5.6.1 SerDes Pre-Emphasis
          7. 6.3.4.5.7  JESD204C Enable
          8. 6.3.4.5.8  Multi-Device Synchronization and Deterministic Latency
          9. 6.3.4.5.9  Operation in Subclass 0 Systems
          10. 6.3.4.5.10 Alarm Monitoring
            1. 6.3.4.5.10.1 Clock Upset Detection
            2. 6.3.4.5.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1  Serializer Test-Mode Details
        2. 6.4.4.2  PRBS Test Modes
        3. 6.4.4.3  Clock Pattern Mode
        4. 6.4.4.4  Ramp Test Mode
        5. 6.4.4.5  Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6  D21.5 Test Mode
        7. 6.4.4.7  K28.5 Test Mode
        8. 6.4.4.8  Repeated ILA Test Mode
        9. 6.4.4.9  Modified RPAT Test Mode
        10. 6.4.4.10 Calibration Modes and Trimming
          1. 6.4.4.10.1 Foreground Calibration Mode
          2. 6.4.4.10.2 Background Calibration Mode
          3. 6.4.4.10.3 Low-Power Background Calibration (LPBG) Mode
        11. 6.4.4.11 Offset Calibration
        12. 6.4.4.12 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
    6. 6.6 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Initialization Set Up
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Sequencing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.2.1 JESD204C Transport Layer Data Formats

The ADC core output samples are formatted in a specific fashion for each JMODE setting based on the transport layer settings for that JMODE. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol definitions used in the JMODE tables is provided in Table 6-20. In all mappings the tail bits (T) are 0 (zero). All samples are formatted as MSB first, LSB last. In JMODEs where N' exceeds the N parameter, the LSBs are set to 0.

Table 6-20 JMODE Table Symbol Definitions
NOTATIONDESCRIPTION
AnSample n from channel A
BnSample n from channel B
CnSample n from channel C
DnSample n from channel D
TTail bits, always set to 0
Table 6-21 JMODE 0 (9-bit, 8/4/2 lanes, 8B/10B)
OCTET 0 1 2 3 4 5 6 7
NIBBLE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 A0[8:0],000 A2[8:0],000 A4[8:0],000 A6[8:0],000 A8[8:0],000 T
D1 A1[8:0],000 A3[8:0],000 A5[8:0],000 A7[8:0],000 A9[8:0],000 T
D2 B0[8:0],000 B2[8:0],000 B4[8:0],000 B6[8:0],000 B8[8:0],000 T
D3 B1[8:0],000 B3[8:0],000 B5[8:0],000 B7[8:0],000 B9[8:0],000 T
D4 (Quad only) C0[8:0],000 C2[8:0],000 C4[8:0],000 C6[8:0],000 C8[8:0],000 T
D5 (Quad only) C1[8:0],000 C3[8:0],000 C5[8:0],000 C7[8:0],000 C9[8:0],000 T
D6 (Quad only) D0[8:0],000 D2[8:0],000 D4,000 D6[8:0],000 D8[8:0],000 T
D7 (Quad only) D1[8:0],000 D3[8:0],000 D5[8:0],000 D7[8:0],000 D9[8:0],000 T
Table 6-22 JMODE 1 (9-bit, 6/3/2 lanes, 8B/10B)
OCTET 0 1
NIBBLE 0 1 2 3
D0 A0[8:0], 000 A1[8:5]
D1 A1[4:0], 000

Dual or Quad: B0[8:1]

Single: 0x00
D2 (Quad or Dual only) B0[0], 000 B1[8:0], 000
D3 (Quad only) C0[8:0], 000 C1[8:5]
D4 (Quad only) C1[4:0], 000 D0[8:1]
D5 (Quad only) D0[0], 000 D1[8:0], 000
Table 6-23 JMODE 2 (8-bit, 4/2/1 lanes, 8B/10B)
OCTET0
NIBBLE01
D0A0
D1 (Dual or Quad only)B0
D2 (Quad only)C0
D3 (Quad only)D0
Table 6-24 JMODE 3 (9-bit, 4/2/1 lanes, 8B/10B)
OCTET 0 1 2 3 4
NIBBLE 0 1 2 3 4 5 6 7 8 9
D0 A0[8:0], 0 A1[8:0], 0 A2[8:0], 0 A3[8:0], 0
D1 (Dual or Quad only) B0[8:0], 0 B1[8:0], 0 B2[8:0], 0 B3[8:0], 0
D2 (Quad only) C0[8:0], 0 C1[8:0], 0 C2[8:0], 0 C3[8:0], 0
D3 (Quad only) D0[8:0], 0 D1[8:0], 0 D2[8:0], 0 D3[8:0], 0
Table 6-25 JMODE 4 (9-bit, 3/2/1lanes, 64B/66B)
OCTET 0 1
NIBBLE 0 1 2 3
D0 A0[8:0], 000 Quad or Dual: B0[8:5]
Single: 0x0
D1 (Dual or Quad only) B0[4:0], 000 Quad: C0[9:1]
Dual: 0x00
D2 (Quad only) C0[0], 000 D0[8:0], 000
Table 6-26 JMODE 5 (8-bit, 2/1/1 lanes, 64B/66B)
OCTET01
NIBBLE0123
D0A0Quad or Dual: B0
Single: 0x00
D1 (Quad Only)C0D0
Table 6-27 JMODE 6 (9-bit, 6/3/2 lanes, 64B/66B)
OCTET 0 1
NIBBLE 0 1 2 3
D0 A0[8:0], 000 A1[8:5]
D1 A1[4:0], 000 Dual or Quad: B0[8:1]
Single: 0x00
D2 (Dual or Quad only) B0[0], 000 B1[8:0], 000
D3 (Quad only) C0[8:0], 000 C1[8:5]
D4 (Quad only) C1[4:0], 000 D0[8:1]
D5 (Quad only) D0[0], 000 D1[8:0], 000
Table 6-28 JMODE 7 (8-bit, 4/2/1 lanes, 64B/66B)
OCTET0
NIBBLE01
D0A0
D1 (Dual or Quad only)B0
D2 (Quad only)C0
D3 (Quad only)D0
Table 6-29 JMODE 8 (12-bit, 4/2/1 lanes, 64B/66B)
OCTET 0 1 2
NIBBLE 0 1 2 3 4 5
D0 A0[8:0], 000 A1[8:0], 000
D1 (Dual or Quad only) B0[8:0], 000 B1[8:0], 000
D2 (Quad only) C0[8:0], 000 C1[8:0], 000
D3 (Quad only) D0[8:0], 000 D1[8:0], 000
Table 6-30 JMODE 9 (8-bit, 8/4/2lanes, 8B/10B)
OCTET0
NIBBLE01
D0A0
D1A1
D2 (Dual or Quad only)B0
D3 (Dual or Quad only)B1
D4 (Quad only)C0
D5 (Quad only)C1
D6 (Quad only)D0
D7 (Quad only)D1
Table 6-31 JMODE 10 (9-bit, 8/4/2 lanes, 8B/10B)
OCTET 0 1 2 3 4
NIBBLE 0 1 2 3 4 5 6 7 8 9
D0 A0[8:0], 0 A2[8:0], 0 A4[8:0], 0 A6[8:0], 0
D1 A1[8:0], 0 A3[8:0], 0 A5[8:0], 0 A7[8:0], 0
D2 (Dual or Quad only) B0[8:0], 0 B2[8:0], 0 B4[8:0], 0 B6[8:0], 0
D3 (Dual or Quad only) B1[8:0], 0 B3[8:0], 0 B5[8:0], 0 B7[8:0], 0
D4 (Quad only) C0[8:0], 0 C2[8:0], 0 C4[8:0], 0 C6[8:0], 0
D5 (Quad only) C1[8:0], 0 C3[8:0], 0 C5[8:0], 0 C7[8:0], 0
D6 (Quad only) D0[8:0], 0 D2[8:0], 0 D4[8:0], 0 D6[8:0], 0
D7 (Quad only) D1[8:0], 0 D3[8:0], 0 D5[8:0], 0 D7[8:0], 0
Table 6-32 JMODE 11 (9-bit, Dual/Single channel only, 8/4 lanes, 8B/10B)
OCTET 0 1 2 3 4 5 6 7
NIBBLE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 A0[8:0], 000 A4[8:0], 000 A8[8:0], 000 A12[8:0], 000 A16[8:0], 000 T
D1 A1[8:0], 000 A5[8:0], 000 A9[8:0], 000 A13[8:0], 000 A17[8:0], 000 T
D2 A2[8:0], 000 A6[8:0], 000 A10[8:0], 000 A14[8:0], 000 A18[8:0], 000 T
D3 A3[8:0], 000 A7[8:0], 000 A11[8:0], 000 A15[8:0], 000 A19[8:0], 000 T
D4 (Dual only) B0[8:0], 000 B4[8:0], 000 B8[8:0], 000 B12[8:0], 000 B16[8:0], 000 T
D5 (Dual only) B1[8:0], 000 B5[8:0], 000 B9[8:0], 000 B13[8:0], 000 B17[8:0], 000 T
D6 (Dual only) B2[8:0], 000 B6[8:0], 000 B10[8:0], 000 B14[8:0], 000 B18[8:0], 000 T
D7 (Dual only) B3[8:0], 000 B7[8:0], 000 B11[8:0], 000 B15[8:0], 000 B19[8:0], 000 T
Table 6-33 JMODE 12 (8-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)
OCTET0
NIBBLE01
D0A0
D1A1
D2A2
D3A3
D4 (Dual only)B0
D5 (Dual only)B1
D6 (Dual only)B2
D7 (Dual only)B3
Table 6-34 JMODE 13 (9-bit, Dual/Single channel only, 8/4lanes, 8B/10B)
OCTET 0 1 2 3 4
NIBBLE 0 1 2 3 4 5 6 7 8 9
D0 A0[8:0], 0 A4[8:0], 0 A8[8:0], 0 A12[8:0], 0
D1 A1[8:0], 0 A5[8:0], 0 A9[8:0], 0 A13[8:0], 0
D2 A2[8:0], 0 A6[8:0], 0 A10[8:0], 0 A14[8:0], 0
D3 A3[8:0], 0 A7[8:0], 0 A11[8:0], 0 A15[8:0], 0
D4 (Dual only) B0[8:0], 0 B4[8:0], 0 B8[8:0], 0 B12[8:0], 0
D5 (Dual only) B1[8:0], 0 B5[8:0], 0 B9[8:0], 0 B13[8:0], 0
D6 (Dual only) B2[8:0], 0 B6[8:0], 0 B10[8:0], 0 B14[8:0], 0
D7 (Dual only) B3[8:0], 0 B7[8:0], 0 B11[8:0], 0 B15[8:0], 0
Table 6-35 JMODE 14 (9-bit, 8/4/2 lanes, 64B/66B)
OCTET 0 1 2
NIBBLE 0 1 2 3 4 5
D0 A0[8:0], 000 A2[8:0], 000
D1 A1[8:0], 000 A3[8:0], 000
D2 (Dual or Quad only) B0[8:0], 000 B2[8:0], 000
D3 (Dual or Quad only) B1[8:0], 000 B3[8:0], 000
D4 (Quad only) C0[8:0], 000 C2[8:0], 000
D5 (Quad only) C1[8:0], 000 C3[8:0], 000
D6 (Quad only) D0[8:0], 000 D2[8:0], 000
D7 (Quad only) D1[8:0], 000 D3[8:0], 000
Table 6-36 JMODE 15 (9-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)
OCTET 0 1 2
NIBBLE 0 1 2 3 4 5
D0 A0[8:0], 000 A4[8:0], 000
D1 A1[8:0], 000 A5[8:0], 000
D2 A2[8:0], 000 A6[8:0], 000
D3 A3[8:0], 000 A7[8:0], 000
D4 (Dual only) B0[8:0], 000 B4[8:0], 000
D5 (Dual only) B1[8:0], 000 B5[8:0], 000
D6 (Dual only) B2[8:0], 000 B6[8:0], 000
D7 (Dual only) B3[8:0], 000 B7[8:0], 000