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ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC)
SBASAL3A
September 2024 – January 2025
ADC3668
,
ADC3669
PRODUCTION DATA
CONTENTS
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ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC)
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics - Power Consumption
6.6
Electrical Characteristics - DC Specifications
6.7
Electrical Characteristics - AC Specifications (ADC3668 - 250 MSPS)
6.8
Electrical Characteristics - AC Specifications (ADC3669 - 500 MSPS)
6.9
Timing Requirements
6.10
Typical Characteristics, ADC3668
6.11
Typical Characteristics, ADC3669
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Analog Inputs
8.3.1.1
Nyquist Zone Selection
8.3.1.2
Analog Front End Design
8.3.2
Sampling Clock Input
8.3.3
Multi-Chip Synchronization
8.3.3.1
SYSREF Monitor
8.3.4
Time-Stamp
8.3.5
Overrange
8.3.6
External Voltage Reference
8.3.7
Digital Gain
8.3.8
Decimation Filter
8.3.8.1
Uncommon Decimation Ratios
8.3.8.2
Decimation Filter Response
8.3.8.3
Decimation Filter Configuration
8.3.8.4
Numerically Controlled Oscillator (NCO)
8.3.9
Digital Interface
8.3.9.1
Parallel LVDS (DDR)
8.3.9.2
Serial LVDS (SLVDS) with Decimation
8.3.9.2.1
SLVDS - Status Bit Insertion
8.3.9.3
Output Data Format
8.3.9.4
32-bit Output Resolution
8.3.9.5
Output Scrambler
8.3.9.6
Output MUX
8.3.9.7
Test Pattern
8.4
Device Functional Modes
8.4.1
Low Latency Mode
8.4.2
Digital Channel Averaging
8.4.3
Power Down Mode
8.5
Programming
8.5.1
GPIO Programming
8.5.2
Register Write
8.5.3
Register Read
8.5.4
Device Programming
8.5.5
Register Map
8.5.6
Detailed Register Description
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Wideband Spectrum Analyzer
9.2.2
Design Requirements
9.2.2.1
Input Signal Path
9.2.2.2
Clocking
9.2.3
Detailed Design Procedure
9.2.3.1
Sampling Clock
9.2.4
Application Performance Plots
9.2.5
Initialization Set Up
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Third-Party Products Disclaimer
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
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Data Sheet
ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC)
1
Features
16-bit, dual channel 250 and 500MSPS ADC
Noise spectral density: -160.4dBFS/Hz
Thermal Noise: 76.4dBFS
Single core (non-interleaved) ADC architecture
Aperture jitter: 75fs
Buffered analog inputs
Programmable 100Ω and 200Ω termination
Input fullscale: 2V
PP
Full power input bandwidth (-3dB): 1.4GHz
Spectral performance (f
IN
= 70MHz, -1dBFS):
SNR: 75.6dBFS
SFDR HD2,3: 80dBc
SFDR worst spur: 94dBFS
INL: ±2 LSB (typical)
DNL: ±0.5 LSB (typical)
Digital down-converters (DDCs)
Up to four independent DDCs
Complex and real decimation
Decimation: /2, /4 to /32768 decimation
48-bit NCO phase coherent frequency hopping
DDR/Serial LVDS interface
16-bit Parallel DDR LVDS for DDC bypass
Serial LVDS for decimation
32-bit output option for high decimation
Power consumption: 300mW/channel (500MSPS)
2
Applications
Software defined radio
Spectrum analyzer
Radar
Spectroscopy
Power amplifier linearization
Communications infrastructure
