SBAU374A May   2021  – May 2022 DAC12DL3200

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Low Latency Evaluation of Receive and Transmit
    2. 1.2 Related Documentation
      1.      Technical Reference Documents
      2.      TSW14DL3200EVM and ADC12DL3200EVM Operation
  4. 2Equipment
    1. 2.1 Evaluation Board Feature Identification Summary
    2. 2.2 Required Equipment
  5. 3Setup Procedure
    1. 3.1  Install the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Install the Configuration GUI Software
    3. 3.3  Connect the DAC12DL3200EVM and TSW14DL3200EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Signal Generators to the EVM (*RF Outputs Disabled Until Directed)
      1. 3.5.1 If External Clocking is Used (Optional)
    6. 3.6  Turn On the TSW14DL3200EVM 12-V Power and Connect to the PC
    7. 3.7  Turn On the DAC12DL3200EVM 5-V Power Supply and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Open the DAC12DL3200EVM GUI and Program the DAC and Clocks for Single Channel, NRZ Mode 2 Operation
    10. 3.10 Open the HSDC Software and Load the FPGA Image to the TSW14DL3200EVM
    11. 3.11 DxSTRB Timing Adjustment
  6. 4Other Modes of Operation
    1. 4.1 Single-Channel RF Mode 2 (2nd Nyquist Zone)
    2. 4.2 Dual-Channel Output Mode 0
    3. 4.3 Dual Channel Mode1 Setup
    4. 4.4 Dual-Channel 2xRF Mode 0 DAC Setup
    5. 4.5 Direct Digital Synthesis Mode
  7. 5Register Log File
  8. 6Device Configuration
    1. 6.1 Tab Organization
    2. 6.2 Low-Level Control
  9.   A Troubleshooting the DAC12DL3200EVM
  10.   B DAC12DL3200EVM Onboard Clocking Configuration

3.3 Connect the DAC12DL3200EVM and TSW14DL3200EVM

With the power off, connect the DAC12DL3200EVM to the TSW14DL3200EVM through the FMC connector as shown in Figure 3-1. Make sure that the standoffs provide the proper height for robust connector connections.

Ensure the board jumpers are configured as follows:

  • JP1 (TXENB) pins 1–2. This enables the DAC outputs.
  • JP2 (SLEEP) pins 2–3. This places the DAC out of sleep mode.
  • JP3 (SYNC) No shunt. This input has an internal pullup. When high, the DAC uses the DxSTRB inputs for strobe. When low, the DAC uses the data LSB as strobe. See the data sheet for more information.
  • JP6 (LMX_CE) pins 1–2. This places the LMX in power down mode (board default).
  • J6 (DAC NCO select) pins 1–2, 4–5, 7–8, 10–11, 13–14, 16–17. Default is all inputs tied to GND.
  • J5, J7–J12 (FTDI Spare GPIOs) No shunt. Default is all inputs disconnected. These jumpers allow for FTDI to control NCO select inputs when installed.