SBAU466 October   2024 DAC39RF10 , TRF1108

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Required Equipment
    2. 2.2 Setup Procedure
      1. 2.2.1  Installing the High Speed Data Converter (HSDC) Pro Software
      2. 2.2.2  Installing the DAC39RF10EVM Configuration GUI Software
      3. 2.2.3  Connect the TRF1108-DAC39RFEVM and TSW14J59EVM
      4. 2.2.4  Connect the Power Supplies to the Boards (Power Off)
      5. 2.2.5  Connect the Spectrum Analyzer to the EVM
      6. 2.2.6  Turn On the TSW14J59EVM Power and Connect to the PC
      7. 2.2.7  Turn On the TRF1108-DAC39RFEVM Power Supplies and Connect to the PC
      8. 2.2.8  Turn On the Signal Generator RF Outputs
      9. 2.2.9  Launch the DAC39RF10EVM GUI and Program the DAC EVM
      10. 2.2.10 Programming the NCO
        1. 2.2.10.1 SPIDAC (NCO only) Operation
      11. 2.2.11 Launch the HSDCpro Software and Load the FPGA Image to the TSW14J59EVM
    3. 2.3 Device Configuration
      1. 2.3.1 Supported JESD204C Device Features
      2. 2.3.2 Tab Organization
      3. 2.3.3 Register Map and Console Control
    4. 2.4 Troubleshooting the TRF1108-DAC39RFEVM
    5. 2.5 Customizing the EVM for Optional Clocking Support
      1. 2.5.1 LMX->DACCLK | LMX/LMK-> FPGA option (Default)
      2. 2.5.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option
      3. 2.5.3 EXT->DACCLK | LMK-> FPGA Clocking Option
    6. 2.6 Signal Routing
    7. 2.7 Jumpers and LEDs
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5References
    1. 5.1 Technical Reference Documents
    2. 5.2 TSW14J59EVM Operation

2.2.5 Connect the Spectrum Analyzer to the EVM

Connect a spectrum analyzer to the OUTA SMA connector of the TRF1108-DAC39RFEVM.

When LMX->DACCLK | LMX/LMK->FPGA Clocking option is Used (Default)

  1. Connect a signal generator to the LMX CLKp input of the EVM. This signal generator must be a low-noise signal generator. Configure the signal generator for the desired clock frequency in the range of 0.8 to 10.24GHz (for this example 10.24GHz is used). For best performance when using an RF signal generator, the power input to the LMX CLKp SMA connector must be 8-10 dBm (2Vpp into 50Ω).
  2. This step is only needed if third clocking option(EXT-> DACLK | LMK->FPGA) is used otherwise skip to next step. Connect a signal generator to the SMA labeled LMK CLKp input of the EVM. This signal is used to generate the necessary FPGA clock signal. Configure the signal generator for the desired (160MHz) clock frequency. Set the output power to approximately 5–7 dBm.
    Note:
    1. The FPGA REF clock frequency can be obtained from the DAC39RF10EVM GUI. Once the DAC39RF10EVM GUI is configured to the desired JMODE mode and clock rate. The Reference Clock frequency required by the EVM is displayed on first page of the GUI shown in Figure 2-3.
    2. Make sure that the DEVCLK and Reference clock sources are frequency-locked using a common 10MHz reference to for functionality.
    3. Do not turn on the RF output of any signal generator at this time.