SBAU466 October   2024 DAC39RF10 , TRF1108

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Required Equipment
    2. 2.2 Setup Procedure
      1. 2.2.1  Installing the High Speed Data Converter (HSDC) Pro Software
      2. 2.2.2  Installing the DAC39RF10EVM Configuration GUI Software
      3. 2.2.3  Connect the TRF1108-DAC39RFEVM and TSW14J59EVM
      4. 2.2.4  Connect the Power Supplies to the Boards (Power Off)
      5. 2.2.5  Connect the Spectrum Analyzer to the EVM
      6. 2.2.6  Turn On the TSW14J59EVM Power and Connect to the PC
      7. 2.2.7  Turn On the TRF1108-DAC39RFEVM Power Supplies and Connect to the PC
      8. 2.2.8  Turn On the Signal Generator RF Outputs
      9. 2.2.9  Launch the DAC39RF10EVM GUI and Program the DAC EVM
      10. 2.2.10 Programming the NCO
        1. 2.2.10.1 SPIDAC (NCO only) Operation
      11. 2.2.11 Launch the HSDCpro Software and Load the FPGA Image to the TSW14J59EVM
    3. 2.3 Device Configuration
      1. 2.3.1 Supported JESD204C Device Features
      2. 2.3.2 Tab Organization
      3. 2.3.3 Register Map and Console Control
    4. 2.4 Troubleshooting the TRF1108-DAC39RFEVM
    5. 2.5 Customizing the EVM for Optional Clocking Support
      1. 2.5.1 LMX->DACCLK | LMX/LMK-> FPGA option (Default)
      2. 2.5.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option
      3. 2.5.3 EXT->DACCLK | LMK-> FPGA Clocking Option
    6. 2.6 Signal Routing
    7. 2.7 Jumpers and LEDs
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5References
    1. 5.1 Technical Reference Documents
    2. 5.2 TSW14J59EVM Operation

2.3.1 Supported JESD204C Device Features

The DAC device supports some configuration of the JESD204C interface. Due to limitations in the TSW14J59EVM firmware, all JESD204C link features of the DAC device are not supported. Table 2-3 lists the supported and non-supported features.

Table 2-3 Supported and Non-Supported Features of the JESD204C Device
JESD204C FeatureSupported by DAC DeviceSupported by TSW14J59EVM
Number of lanes per link (L)L = 1, 2, 3, 4, 6, 8,12,16(1)L = 1, 2, 3, 4, 6, 8,12,16 supported
ScramblingSupportedSupported
Test patternsPRBS7, PRBS9, PRBS15, PRBS31Not Supported
SpeedLane rates from 0.75 to 12.8 GbpsLane rates from 2 to 17.16 Gbps
ƒ(SAMPLE) parameter must be properly set in HSDC Pro GUI.
(1) Dependent on bypass or decimation mode and output rate selection. Always disable the JESD204 block before changing any of the JESD204C settings. Once the settings are changed, re-enable the JESD204 block.