SBAU466 October   2024 DAC39RF10 , TRF1108

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Required Equipment
    2. 2.2 Setup Procedure
      1. 2.2.1  Installing the High Speed Data Converter (HSDC) Pro Software
      2. 2.2.2  Installing the DAC39RF10EVM Configuration GUI Software
      3. 2.2.3  Connect the TRF1108-DAC39RFEVM and TSW14J59EVM
      4. 2.2.4  Connect the Power Supplies to the Boards (Power Off)
      5. 2.2.5  Connect the Spectrum Analyzer to the EVM
      6. 2.2.6  Turn On the TSW14J59EVM Power and Connect to the PC
      7. 2.2.7  Turn On the TRF1108-DAC39RFEVM Power Supplies and Connect to the PC
      8. 2.2.8  Turn On the Signal Generator RF Outputs
      9. 2.2.9  Launch the DAC39RF10EVM GUI and Program the DAC EVM
      10. 2.2.10 Programming the NCO
        1. 2.2.10.1 SPIDAC (NCO only) Operation
      11. 2.2.11 Launch the HSDCpro Software and Load the FPGA Image to the TSW14J59EVM
    3. 2.3 Device Configuration
      1. 2.3.1 Supported JESD204C Device Features
      2. 2.3.2 Tab Organization
      3. 2.3.3 Register Map and Console Control
    4. 2.4 Troubleshooting the TRF1108-DAC39RFEVM
    5. 2.5 Customizing the EVM for Optional Clocking Support
      1. 2.5.1 LMX->DACCLK | LMX/LMK-> FPGA option (Default)
      2. 2.5.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option
      3. 2.5.3 EXT->DACCLK | LMK-> FPGA Clocking Option
    6. 2.6 Signal Routing
    7. 2.7 Jumpers and LEDs
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5References
    1. 5.1 Technical Reference Documents
    2. 5.2 TSW14J59EVM Operation

3.2 PCB Layouts

TRF1108-DAC39RFEVM Layout SuggestionsFigure 3-2 Layout Suggestions

Any high frequency board presents unique challenges for implementation. The DAC39RF10 presents a maximum sampling rate of 20.48 GSPS. Therefore, the first nyquist of this device is 10.24GHz. Care must be taken when laying out this design.

On the TRF1108-DAC39RFEVM, the analog front end is an example of this. First, the trace widths and distances to the top ground plane must be carefully chosen to present as 50Ohm transmission lines. Stitching vias are recommended at <1/8th wavelength distance from each other to connect the top ground plane to the adjacent ground plane. The 9dB pad is also located as close to the DAC output as physically possible.

TRF1108-DAC39RFEVM RF Ground PlaneFigure 3-3 RF Ground Plane

The ground plane directly adjacent to the top plane is uninterrupted underneath the RF trace. This prevents excess inductance and thus incorrect impedance of the RF trace.

TRF1108-DAC39RFEVM Layer StackupFigure 3-4 Layer Stackup

The layer stackup, especially dielectric between the RF and RF ground layer must be optimized for controlled dielectric constant. Here, the dialectric was chosen as Panasonic Megtron6, with a highly controlled dielectric constant of 3.6.

Additionally, the solder mask layer was omitted from on top of and directly adjacent to the RF trace. This is because this layer often includes uncontrolled properties and, thus is generally not recommended to be included directly on high frequency lines.