SBAU466 October   2024 DAC39RF10 , TRF1108

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Required Equipment
    2. 2.2 Setup Procedure
      1. 2.2.1  Installing the High Speed Data Converter (HSDC) Pro Software
      2. 2.2.2  Installing the DAC39RF10EVM Configuration GUI Software
      3. 2.2.3  Connect the TRF1108-DAC39RFEVM and TSW14J59EVM
      4. 2.2.4  Connect the Power Supplies to the Boards (Power Off)
      5. 2.2.5  Connect the Spectrum Analyzer to the EVM
      6. 2.2.6  Turn On the TSW14J59EVM Power and Connect to the PC
      7. 2.2.7  Turn On the TRF1108-DAC39RFEVM Power Supplies and Connect to the PC
      8. 2.2.8  Turn On the Signal Generator RF Outputs
      9. 2.2.9  Launch the DAC39RF10EVM GUI and Program the DAC EVM
      10. 2.2.10 Programming the NCO
        1. 2.2.10.1 SPIDAC (NCO only) Operation
      11. 2.2.11 Launch the HSDCpro Software and Load the FPGA Image to the TSW14J59EVM
    3. 2.3 Device Configuration
      1. 2.3.1 Supported JESD204C Device Features
      2. 2.3.2 Tab Organization
      3. 2.3.3 Register Map and Console Control
    4. 2.4 Troubleshooting the TRF1108-DAC39RFEVM
    5. 2.5 Customizing the EVM for Optional Clocking Support
      1. 2.5.1 LMX->DACCLK | LMX/LMK-> FPGA option (Default)
      2. 2.5.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option
      3. 2.5.3 EXT->DACCLK | LMK-> FPGA Clocking Option
    6. 2.6 Signal Routing
    7. 2.7 Jumpers and LEDs
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5References
    1. 5.1 Technical Reference Documents
    2. 5.2 TSW14J59EVM Operation

2.5.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option

The TRF1108-DAC39RFEVM can be configured to use EXT->DACCLK | LMX/LMK-> FPGA Clocking option. Similar to above use case The user provide a single high frequency (10-15 dBm) signal to an SMA labeled LMX CLKp. This signal is routed though the splitter to Balun and LMX1204. The Balun converts the single ended signal into differential and is used to clock the DAC. The second output from the splitter is used by LMX1204 which generates the low frequency DAC SYSERF signal, FPGA reference clocks and FPGA SYSREF signal. The FPGA reference clocks and FPGA SYSREF signal are feed into the CLKIN1 and CLKIN0 of LMK04828. The LMK04828 and is used in clock distribution mode and provides several copies/divided down version of FPGA reference clock and FPGA SYSREF signal. The block diagram of clocking option is shown in Figure 2-14.

The EVM can be configured to use onboard clocking option with the following steps:

  • Remove C141 and C142, populate C136 and C139
  • Remove C138 and C140, populate C134 and C135
  • Remove C75 and C76, populate C73 and C74

TRF1108-DAC39RFEVM EXT->DACCLK | LMX/LMK-> FPGA Clocking System Block DiagramFigure 2-14 EXT->DACCLK | LMX/LMK-> FPGA Clocking System Block Diagram