Design Goals

Design Description

This high-side, current sensing circuit uses one comparator with a rail-to-rail input common-mode range to create an overcurrent alert (OC-Alert) signal at the comparator output (COMP OUT) if the load current rises above 1A. The OC-Alert signal in this implementation is active low. So when the 1A threshold is exceeded, the comparator output goes low. Hysteresis is implemented such that OC-Alert returns to a logic high state when the load current reduces to 0.5A (a 50% reduction). This circuit utilizes an open-drain output comparator to level shift the output high logic level for controlling a digital logic input pin. For applications needing to drive the gate of a MOSFET switch, a comparator with a push-pull output is preferred.

Design Notes

1. Select a comparator with rail-to-rail input common-mode range to enable high-side current sensing.
2. Select a comparator with an open-drain output stage for level-shifting.
3. Select a comparator with low input offset voltage to optimize accuracy.
4. Calculate the value for the shunt resistor (R₆) so the shunt voltage (V_SHUNT) is at least ten times larger than the comparator offset voltage (V_IO).

Design Steps

1. Select the value of R₆ so V_SHUNT is at least 10 times greater than the comparator input offset voltage (V_IO). Making R₆ very large improves OC detection accuracy but reduces supply headroom.
   ${\mathrm{V}}_{\mathrm{SHUNT}}=\left({\mathrm{I}}_{\mathrm{OC}}\times {\mathrm{R}}_6\right)\ge 10\times {\mathrm{V}}_{\mathrm{IO}}=55\mathrm{mV}$
   $\mathrm{set}{\mathrm{R}}_6=100\mathrm{m\Omega }\mathrm{for}{\mathrm{I}}_{\mathrm{OC}}=1\mathrm{A}and{\mathrm{V}}_{\mathrm{IO}}=5.5\mathrm{mV}$
2. Determine the desired switching thresholds for when the comparator output transitions from high-to-low (V_L) and low-to-high (V_H). V_L represents the threshold when the load current crosses the OC level, while V_H represents the threshold when the load current recovers to a normal operating level.
   ${\mathrm{V}}_{\mathrm{L}}={\mathrm{V}}_{\mathrm{S}}-\left({\mathrm{I}}_{\mathrm{OC}}\times {\mathrm{R}}_6\right)=10-(1\times 0.1)=9.9\mathrm{V}$
   ${\mathrm{V}}_{\mathrm{H}}={\mathrm{V}}_{\mathrm{S}}-\left({\mathrm{I}}_{\mathrm{RC}}\times {\mathrm{R}}_6\right)=10-(0.5\times 0.1)=9.95\mathrm{V}$
   
3. With the non-inverting input pin of the comparator labeled as V_TH and the comparator output in a logic low state (ground), derive an equation for V_TH where V_H represents the load voltage (V_LOAD) when the comparator output transitions from low to high. Note that the simplified diagram for deriving the equation shows the comparator output as ground (logic low).
   
   ${\mathrm{V}}_{\mathrm{TH}}={\mathrm{V}}_{\mathrm{H}}\times \left(\frac{{\mathrm{R}}_2}{{\mathrm{R}}_1+{\mathrm{R}}_2}\right)$
4. With the non-inverting input pin of the comparator labeled as V_TH and the comparator output in a high-impedance state, derive an equation for V_TH where V_L represents the load voltage (V_LOAD) when the comparator output transitions from high to low. Applying superposition theory to solve for V_TH is recommended.
   
   ${\mathrm{V}}_{\mathrm{TH}}={\mathrm{V}}_{\mathrm{L}}\times \left(\frac{{\mathrm{R}}_2+{\mathrm{R}}_3}{{\mathrm{R}}_1+{\mathrm{R}}_2+{\mathrm{R}}_3}\right)+{\mathrm{V}}_{\mathrm{PU}}\times \left(\frac{{\mathrm{R}}_1}{{\mathrm{R}}_1+{\mathrm{R}}_2+{\mathrm{R}}_3}\right)$
5. Eliminate variable V_TH by setting the two equations equal to each other and solve for R₁. The result is the following quadratic equation. Solving for R₂ is less desirable since there are more standard values for small resistor values than the larger ones.
   $0=\left({\mathrm{V}}_{\mathrm{PU}}\right)\times {{\mathrm{R}}_1}^2+({\mathrm{V}}_{\mathrm{PU}}\times {\mathrm{R}}_2+{\mathrm{V}}_{\mathrm{L}}\times ({\mathrm{R}}_3+{\mathrm{R}}_2)-{\mathrm{V}}_{\mathrm{H}}\times {\mathrm{R}}_2)\times {\mathrm{R}}_1+({\mathrm{V}}_{\mathrm{L}}-{\mathrm{V}}_{\mathrm{H}})\times ({{\mathrm{R}}_2}^2+{\mathrm{R}}_2\times {\mathrm{R}}_3)$
6. Select values for R3 and R2. R₃ is significantly smaller than R₂ (R₃ << R₂). Avoid increasing R₃ since an increase in R₃ causes the comparator logic high-output level to increase beyond V_PU. For example, increasing R₃ to a value of 100kΩ can cause the logic high output to be 3.6V. In this case, select R₂ = 2M and R₃ = 1kΩ.
   
   ${\mathrm{R}}_2=2\mathrm{M\Omega }$
   ${\mathrm{R}}_3=1\mathrm{k\Omega }$
7. Calculate R₁ after substituting in numeric values for V_PU, R₂, V_L, V_H, and R₃. For this design, set V_PU = 3.3, R₂ = 2M, V_L = 9.9, V_H = 9.95, and R₃ = 1kΩ.
   $0=\left(3.3\right)\times {{\mathrm{R}}_1}^2+(6.591\mathrm{M})\times {\mathrm{R}}_1-(200.1\mathrm{G})$
   $\mathrm{the}\mathrm{positive}\mathrm{root}\mathrm{for}{\mathrm{R}}_1=29.9\mathrm{k\Omega }$
   $\mathrm{using}\mathrm{standard}1\%\mathrm{resistor}\mathrm{values},{\mathrm{R}}_1=30.1\mathrm{k\Omega }$
8. Calculate V_TH using the equation derived in Design Step 3; use the calculated value for R₁. Note that V_TH is less than V_L since V_PU is less that V_L.
   ${\mathrm{V}}_{\mathrm{TH}}={\mathrm{V}}_{\mathrm{H}}\times \left(\frac{{\mathrm{R}}_2}{{\mathrm{R}}_1+{\mathrm{R}}_2}\right)=9.802\mathrm{V}$
9. With the inverting terminal labeled as V_TH, derive an equation for V_TH in terms of R₄, R₅, and V_S.
   ${\mathrm{V}}_{\mathrm{TH}}={\mathrm{V}}_{\mathrm{S}}\times \left(\frac{{\mathrm{R}}_5}{{\mathrm{R}}_4+{\mathrm{R}}_5}\right)$
10. Calculate R₄ after substituting in numeric values R₅ = 1M, V_S = 10, and the calculated value for V_TH.
    ${\mathrm{R}}_4=\left(\frac{{\mathrm{R}}_5\times ({\mathrm{V}}_{\mathrm{S}}-{\mathrm{V}}_{\mathrm{TH}})}{{\mathrm{V}}_{\mathrm{TH}}}\right)=20.15\mathrm{k\Omega }$
    $\mathrm{using}\mathrm{standard}1\%\mathrm{resistor}\mathrm{values},{\mathrm{R}}_4=20.5\mathrm{k\Omega }$

Design Simulations

DC Simulation Results

Transient Simulation Results

Design References

See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

See Circuit SPICE Simulation File SLOM456.

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