TMCS110x Layout Challenges and Best Practices
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1 Introduction
This application note begins with a discussion of device operation and device specifications. The document continues with best practices for the TMCS110x product family, including grounding techniques, output stage limitations, as well as various sources of external fields and how to combat them.
2 Device Operation
To better comprehend what affects measurement errors with a Hall-based current sensor like the TMCS1100, understanding how the device operates in a general sense is helpful. TMCS1100 Operation Diagram illustrates how current flows through the copper lead frame of the device. As the current flows from IN+ to IN–, a magnetic field is generated in accordance with Ampere's law. This magnetic field produces a voltage potential change on sensors located in the center of the lead frame via the Hall-effect . This potential is then scaled, sampled by the sampling integrator, and sent to the output pin of the device. Note that the positive polarity of the magnetic coupling factor as current flows from IN+ to IN– is a magnetic field generated downward into the sensor, denoted in this paper as the negative z direction.
For any given TMCS110x device, there are typically multiple sensitivity variants. For the TMCS1100, the sensitivities include 50 mV/A, 100 mV/A, 200 mV/A, and 400 mV/A. For each device, the lead frame and the Hall stage are the same for all variants within some manufacturing tolerance.
3 Grounding
A key feature of the TMCS110x device family is temperature compensation. This allows a given TMCS110x device to achieve a low-sensitivity drift of ±0.5% over temperature and lifetime. This compensation is achieved through internal circuitry that utilizes a clock, which contains pulsing components, and therefore requires a properly-designed ground path. While a low-resistance path between device ground and the central system ground is a good practice in general, the digital clock provides a dynamic current component that can further influence measurement precision. Therefore, Equation 2 is used to approximate what kind of offset might be observed for a given device ground to system ground return path, where the values of resistance and inductance are quantifiable from the planes or traces between the GND pin of the TMCS1100 and the system ground.
As the path to system ground becomes more complex, the effect of these artifacts becomes more apparent as added offset and noise on the output of the device. To demonstrate this, a long, discrete coiled wire was used in place of the ground plane on a TMCS1100EVM to emulate a long trace between the GND pin and system GND of the module. In addition, the bypass capacitor was also removed from the EVM to provide a worst-case look at the effects of these artifacts on the device. TMCS1100EVM With "Poor" Inductive Ground Path shows the output of the A2 device variant in this state, with no input current supplied to the device.
Figure 3-1 TMCS1100EVM With "Poor" Inductive
Ground PathAn ideal grounding path is a direct path from the GND pin of the device to the system GND of the board, using as wide of a trace as possible to minimize resistance and inductance between the connection points. A GND plane as used on the TMCS1100EVM is ideal. TMCS1100EVM Default "Good" Ground Path shows the output of the A1 variant under ideal grounding conditions.
Figure 3-2 TMCS1100EVM Default "Good" Ground
PathNote that the "good" ground of the device still retains bouncing artifacts. This is expected as systematic noise comes from the sampling integrator used to compensate for temperature and lifetime drift, and is discussed in depth in the next section. In most designs, a wide ground plane as mentioned is not always achievable, but consideration must be given to how the device GND pin interfaces with the true ground of the system for best performance.
