The PGA855 architecture consists of a high-speed current-feedback input stage with an internally matched gain resistor network, followed by a four-resistor, fully differential amplifier output stage. Eight preprogrammed binary gains, from 0.125V/V to 16V/V are selectable using gain-select pins A0, A1, and A2. Each amplifier in the circuit has a corresponding amplifier voltage noise and current noise contribution. In addition, each resistor in the gain resistor network has a thermal noise contribution element. Figure 7-13 shows a functional block diagram for the PGA855 and the noise sources.

Figure 4-1 Noise Sources for PGA855

In the case of the PGA855, the voltage noise contribution of the internal amplifiers and the thermal noise contributions from the internal gain resistor network are lumped into a single voltage noise source e_NI. The input stage amplifier current noise is kept as a separate current noise source at the input of the PGA855. Since the resistor network changes of each gain setting, the PGA855 data sheet provides separate referred-to-input (RTI) voltage noise density specifications for each gain setting from 0.125V/V to 16V/V respectively. Figure 7-13 shows the simplified noise model of the PGA855.

Figure 4-2 Simplified Noise Model for PGA855

The simplified PGA855 model uses a single stage model; where all the noise specifications are referred to the amplifier input. The input current noise remains constant across all gains. To refer the noise to the device output, the designer needs to multiply the input-referred noise by the PGA gain. Equation 4 provides the calculation of the output-referred noise, e_N(RTO) as a function of the PGA gain, G.