The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
PGA112, PGA113 | VSSOP (10) | 3.00 mm × 3.00 mm |
PGA116, PGA117 | TSSOP (20) | 6.50 mm × 4.40 mm |
Changes from B Revision (September 2008) to C Revision
DEVICE | NO. OF MUX INPUTS | GAINS (EIGHT EACH) |
SPI DAISY-CHAIN | SHUTDOWN | PACKAGE | |
---|---|---|---|---|---|---|
HARDWARE | SOFTWARE | |||||
PGA112 | 2 | Binary | No | No | ✓ | VSSOP-10 |
PGA113 | 2 | Scope | No | No | ✓ | VSSOP-10 |
PGA116 | 10 | Binary | ✓ | ✓ | ✓ | TSSOP-20 |
PGA117 | 10 | Scope | ✓ | ✓ | ✓ | TSSOP-20 |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | AVDD | I | Analog supply voltage (2.2 V to 5.5 V) |
2 | CH1 | I | Input MUX channel 1 |
3 | VCAL/CH0 | I | Input MUX channel 0 and VCAL input. For system calibration purposes, connect this pin to a low-impedance external reference voltage to use internal calibration channels. The four internal calibration channels are connected to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL is loaded with 100 kΩ (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise, VCAL/CH0 appears as high impedance. |
4 | VREF | I | Reference input pin. Connect external reference for VOUT offset shift or to midsupply for midsupply referenced systems. VREF must be connected to a low-impedance reference capable of sourcing and sinking at least 2 mA or VREF must be connected to GND. |
5 | VOUT | O | Analog voltage output. When AVDD < DVDD, VOUT is clamped to AVDD + 300 mV. |
6 | GND | — | Ground pin |
7 | SCLK | I | Clock input for SPI serial interface |
8 | DIO | I | Data input/output for SPI serial interface. DIO contains a weak, 10-μA internal pulldown current source. |
9 | CS | I | Chip select line for SPI serial interface |
10 | DVDD | I | Digital and op amp output stage supply voltage (2.2 V to 5.5 V). Useful in multi-supply systems to prevent overvoltage and lockup condition on an analog-to-digital (ADC) input (for example, a microcontroller with an ADC running on 3 V and the PGA powered from 5 V). Digital I/O levels to be relative to DVDD. DVDD should be bypassed with a 0.1-μF ceramic capacitor, and DVDD must supply the current for the digital portion of the PGA as well as the load current for the op amp output stage. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | AVDD | I | Analog supply voltage (2.2 V to 5.5 V) |
2 | CH5 | I | Input MUX channel 5 |
3 | CH4 | I | Input MUX channel 4 |
4 | CH3 | I | Input MUX channel 3 |
5 | CH2 | I | Input MUX channel 2 |
6 | CH1 | I | Input MUX channel 1 |
7 | VCAL/CH0 | I | Input MUX channel 0 and VCAL input. For system calibration purposes, connect this pin to a low-impedance external reference voltage to use internal calibration channels. The four internal calibration channels are connected to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL is loaded with 100 kΩ (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise, VCAL/CH0 appears as high impedance. |
8 | VREF | I | Reference input pin. Connect external reference for VOUT offset shift or to midsupply for midsupply referenced systems. VREF must be connected to a low-impedance reference capable of sourcing and sinking at least 2 mA or to GND. |
9 | VOUT | O | Analog voltage output. When AVDD < DVDD, VOUT is clamped to AVDD + 300 mV. |
10 | CH7 | I | Input MUX channel 7 |
11 | CH8 | I | Input MUX channel 8 |
12 | CH9 | I | Input MUX channel 9 |
13 | ENABLE | I | Hardware enable pin. Logic low puts the part into Shutdown mode (IQ < 1 μA). |
14 | GND | — | Ground pin |
15 | SCLK | I | Clock input for SPI serial interface |
16 | DIN | I | Data input for SPI serial interface. DIN contains a weak, 10-μA internal pulldown current source to allow for ease of daisy-chain configurations. |
17 | DOUT | O | Data output for SPI serial interface. DOUT goes to high-Z state when CS goes high for standard SPI interface. |
18 | CS | I | Chip select line for SPI serial interface |
19 | DVDD | I | Digital and op amp output stage supply voltage (2.2 V to 5.5 V). Useful in multi-supply systems to prevent overvoltage and lockup condition on an ADC input (for example, a microcontroller with an ADC running on 3 V and the PGA powered from 5 V). Digital I/O levels to be relative to DVDD. DVDD should be bypassed with a 0.1-μF ceramic capacitor, and DVDD must supply the current for the digital portion of the PGA as well as the load current for the op amp output stage. |
20 | CH6 | I | Input MUX channel 6 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | 7 | V | ||
Signal input terminals, voltage(2) | GND – 0.5 | AVDD + 0.5 | V | |
Signal input terminals, current(2) | ±10 | mA | ||
Output short circuit | Continuous | |||
Operating temperature | –40 | 125 | °C | |
Junction temperature | 150 | °C | ||
Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
Machine Model (MM) | ±300 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD | 2.2 | 5 | 5.5 | V | |
DVDD | 2.2 | 5 | 5.5 | V | |
Operating temperature | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | PGA112, PGA113 | PGA116, PGA117 | UNIT | |
---|---|---|---|---|
DGS (VSSOP) | PW (TSSOP) | |||
10 PINS | 20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 98.3 | 100.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 57 | 36.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 51.2 | 50.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.3 | 2.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 36.9 | 50.2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4.8 | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | ||||||||
Input offset voltage | VOS | AVDD = DVDD = 5 V, VREF = VIN = AVDD/2, VCM = 2.5 V | ±25 | ±100 | μV | |||
AVDD = DVDD = 5 V, VREF = VIN = AVDD/2, VCM = 4.5 V | ±75 | ±325 | μV | |||||
vs temperature, –40°C to 125°C | dVOS/dT | AVDD = DVDD = 5 V, VCM = 2.5 V | TA = –40°C to 125°C | 0.35 | 1.2 | μV/°C | ||
vs temperature, –40°C to 85°C | AVDD = DVDD = 5 V, VCM = 2.5 V | 0.15 | 0.9 | μV/°C | ||||
vs temperature, –40°C to 125°C | AVDD = DVDD = 5 V, VCM = 4.5 V | TA = –40°C to 125°C | 0.6 | 1.8 | μV/°C | |||
vs temperature, –40°C to 85°C | AVDD = DVDD = 5 V, VCM = 4.5 V | 0.3 | 1.3 | μV/°C | ||||
vs power supply | PSRR | AVDD = DVDD = 2.2 V to 5.5 V, VCM = 0.5 V, VREF = VIN = AVDD/2 |
5 | 20 | μV/V | |||
Over temperature, –40°C to 125°C | AVDD = DVDD = 2.2 V to 5.5 V, VCM = 0.5 V, VREF = VIN = AVDD/2 |
TA = –40°C to 125°C | 5 | 40 | μV/V | |||
INPUT ON-CHANNEL CURRENT | ||||||||
Input on-channel current (Ch0, Ch1) | IIN | VREF = VIN = AVDD/2 | ±1.5 | ±5 | nA | |||
Over temperature, –40°C to 125°C | VREF = VIN = AVDD/2 | See Typical Characteristics | nA | |||||
INPUT VOLTAGE RANGE | ||||||||
Input voltage range(1) | IVR | GND – 0.1 | AVDD + 0.1 | V | ||||
Overvoltage input range | No output phase reversal(2) | GND – 0.3 | AVDD + 0.3 | V | ||||
INPUT IMPEDANCE (Channel On)(3) | ||||||||
Channel input capacitance | CCH | 2 | pF | |||||
Channel switch resistance | RSW | 150 | Ω | |||||
Amplifier input capacitance | CAMP | 3 | pF | |||||
Amplifier input resistance | RAMP | Input resistance to GND | 10 | GΩ | ||||
VCAL/CH0 | RIN | CAL1 or CAL2 selected | 100 | kΩ | ||||
GAIN SELECTIONS | ||||||||
Nominal gains | Binary gains: 1, 2, 4, 8, 16, 32, 64, 128 | 1 | 128 | |||||
Scope gains: 1, 2, 5, 10, 20, 50, 100, 200 | 1 | 200 | ||||||
DC gain error | G = 1 | VOUT = GND + 85 mV to DVDD – 85 mV | 0.006% | 0.1% | ||||
1 < G ≤ 32 | VOUT = GND + 85 mV to DVDD – 85 mV | 0.1% | ||||||
G ≥ 50 | VOUT = GND + 85 mV to DVDD – 85 mV | 0.3% | ||||||
DC gain drift | G = 1 | VOUT = GND + 85 mV to DVDD – 85 mV | TA = –40°C to 125°C | 0.5 | ppm/°C | |||
1 < G ≤ 32 | VOUT = GND + 85 mV to DVDD – 85 mV | TA = –40°C to 125°C | 2 | ppm/°C | ||||
G ≥ 50 | VOUT = GND + 85 mV to DVDD – 85 mV | TA = –40°C to 125°C | 6 | ppm/°C | ||||
CAL2 DC gain error(4) | Op Amp + Input = 0.9 VCAL, VREF = VCAL = AVDD/2, G = 1 |
0.02% | ||||||
CAL2 DC gain drift(4) | Op Amp + Input = 0.9 VCAL, VREF = VCAL = AVDD/2, G = 1 |
TA = –40°C to 125°C | 2 | ppm/°C | ||||
CAL3 DC gain error(4) | Op Amp + Input = 0.1 VCAL, VREF = VCAL = AVDD/2, G = 1 |
0.02% | ||||||
CAL3 DC gain drift(4) | Op Amp + Input = 0.1 VCAL, VREF = VCAL = AVDD/2, G = 1 |
TA = –40°C to 125°C | 2 | ppm/°C | ||||
INPUT IMPEDANCE (CHANNEL OFF)(3) | ||||||||
Input impedance | CCH | See Figure 55 | 2 | pF | ||||
INPUT OFF-CHANNEL CURRENT | ||||||||
Input Off-Channel Current (Ch0, Ch1)(5) | ILKG | VREF = GND, VOFF-CHANNEL = AVDD/2, VON-CHANNEL = AVDD/2 – 0.1 V |
±0.05 | ±1 | nA | |||
Over temperature, –40°C to 125°C | VREF = GND, VOFF-CHANNEL = AVDD/2, VON-CHANNEL = AVDD/2 – 0.1 V |
See Typical Characteristics | ||||||
Channel-to-Channel Crosstalk | 130 | dB | ||||||
OUTPUT | ||||||||
Voltage output swing from rail | IOUT = ±0.25 mA, AVDD ≥ DVDD(7) | GND + 0.05 | DVDD – 0.05 | V | ||||
IOUT = ±5 mA, AVDD ≥ DVDD(7) | GND + 0.25 | DVDD – 0.25 | V | |||||
DC output nonlinearity | VOUT = GND + 85 mV to DVDD – 85 mV(6) | 0.0015 | %FSR | |||||
Short circuit current | ISC | –30/+60 | mA | |||||
Capacitive load drive | CLOAD | See Typical Characteristics | ||||||
NOISE | ||||||||
Input voltage noise density | en | f > 10 kHz, CL = 100 pF, VS = 5 V | 12 | nV/√Hz | ||||
f > 10 kHz, CL = 100 pF, VS = 2.2 V | 22 | nV/√Hz | ||||||
Input voltage noise | en | f = 0.1 Hz to 10 Hz, CL = 100 pF, VS = 5 V | 0.362 | μVPP | ||||
f = 0.1 Hz to 10 Hz, CL = 100 pF, VS = 2.2 V | 0.736 | μVPP | ||||||
Input current density | In | f = 10 kHz, CL = 100 pF | 400 | fA/√Hz | ||||
SLEW RATE | ||||||||
Slew rate | SR | See Table 1 | V/μs | |||||
SETTLING TIME | ||||||||
Settling time | tS | See Table 1 | μs | |||||
FREQUENCY RESPONSE | ||||||||
Frequency response | See Table 1 | MHz | ||||||
THD + NOISE | ||||||||
G = 1, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.003% | |||||||
G = 10, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.005% | |||||||
G = 50, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.03% | |||||||
G = 128, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.08% | |||||||
G = 200, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.1% | |||||||
G = 1, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.02% | |||||||
G = 10, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.01% | |||||||
G = 50, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.03% | |||||||
G = 128, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.08% | |||||||
G = 200, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF | 0.11% | |||||||
POWER SUPPLY | ||||||||
Operating voltage range(7) | AVDD | 2.2 | 5.5 | V | ||||
DVDD | 2.2 | 5.5 | V | |||||
Quiescent current analog | IQA | IO = 0, G = 1, VOUT = VREF | 0.33 | 0.45 | mA | |||
Over temperature, –40°C to 125°C | TA = –40°C to 125°C | 0.45 | mA | |||||
Quiescent current digital(8)(9)(10) | IQD | IO = 0, G = 1, VOUT = VREF, SCLK at 10 MHz, CS = Logic 0, DIO or DIN = Logic 0 |
0.75 | 1.2 | mA | |||
Over temperature, –40°C to 125°C(8)(9)(10) | IO = 0, G = 1, VOUT = VREF, SCLK at 10 MHz, CS = Logic 0, DIO or DIN = Logic 0 |
TA = –40°C to 125°C | 1.2 | mA | ||||
Shutdown current analog + digital(8)(9) | ISDA + ISDD | IO = 0, VOUT = VREF, G = 1, SCLK Idle | 4 | μA | ||||
IO = 0, VOUT = 0, G = 1, SCLK at 10MHz, CS = Logic 0, DIO or DIN = Logic 0 |
245 | μA | ||||||
POWER-ON RESET (POR) | ||||||||
POR trip voltage | Digital interface disabled and Command Register set to POR values for DVDD < POR Trip Voltage | 1.6 | V | |||||
TEMPERATURE RANGE | ||||||||
Specified range | –40 | 125 | °C | |||||
Operating range | –40 | 125 | °C | |||||
Thermal resistance | θJA | |||||||
VSSOP-10 | 164 | °C/W | ||||||
DIGITAL INPUTS (SCLK, CS, DIO, DIN) | ||||||||
Logic low | 0 | 0.3DVDD | V | |||||
Input leakage current (SCLK and CS only) | –1 | 1 | μA | |||||
Weak pulldown current (DIO, DIN only) | 10 | μA | ||||||
Logic high | 0.7DVDD | DVDD | V | |||||
Hysteresis | 700 | mV | ||||||
DIGITAL OUTPUT (DIO, DOUT) | ||||||||
Logic high | IOH = –3 mA (sourcing) | DVDD – 0.4 | DVDD | V | ||||
Logic low | IOL = 3 mA (sinking) | GND | GND + 0.4 | V | ||||
CHANNEL AND GAIN TIMING | ||||||||
Channel select time | 0.2 | μs | ||||||
Gain select time | 0.2 | μs | ||||||
SHUTDOWN MODE TIMING | ||||||||
Enable time | 4 | μs | ||||||
Disable time | VOUT goes high-impedance, RF and RI remain connected between VOUT and VREF | 2 | μs | |||||
POWER-ON-RESET (POR) TIMING | ||||||||
POR power-up time | DVDD ≥ 2 V | 40 | μs | |||||
POR power-down time | DVDD ≤ 1.5 V | 5 | μs |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Input capacitance (SCLK, CS, and DIO pins) | 1 | pF | ||||
tRFI | Input rise and fall time(1)
(CS, SCLK, and DIO pins) |
2 | μs | |||
tRFO | Output rise and fall time (DIO pin)(1) | CLOAD = 60 pF | 10 | ns | ||
tCSH | CS high time (CS pin)(1) | 40 | ns | |||
tCSO | SCLK edge to CS fall setup time(1) | 10 | ns | |||
tCSSC | CS fall to first SCLK edge setup time | 10 | ns | |||
fSCLK | SCLK Frequency(2) | 10 | MHz | |||
tHI | SCLK high time(3) | 40 | ns | |||
tLO | SCLK low time(3) | 40 | ns | |||
tSCCS | SCLK last edge to CS rise setup time(1) | 10 | ns | |||
tCS1 | CS rise to SCLK edge setup time(1) | 10 | ns | |||
tSU | DIN setup time | 10 | ns | |||
tHD | DIN hold time | 10 | ns | |||
tDO | SCLK to DOUT valid propagation delay(1) | 25 | ns | |||
tSOZ | CS rise to DOUT forced to Hi-Z(1) | 20 | ns |
The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in an 10-pin VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
The PGA uses a SPI interface with daisy-chain capability, a standard serial peripheral interface (SPI). Both SPI Mode 0,0 and Mode 1,1 are supported, as shown in Figure 56 and described in Table 2.
Featuring low offset, low offset drift and low noise, the PGA11x series provides a flexible analog building block for a variety of applications. The PGA112 and PGA116 offer binary gains of 1, 2, 4, 8, 16, 32, 64, 128 and a 2 channel MUX while the PGA113 and PGA117 offer scope gains of 1, 2, 5, 10, 20, 50, 100, 200 and a 10 channel MUX.
The PGA112 and PGA113 devices have a software shutdown mode, and the PGA116 and PGA117 devices offer both a hardware and software shutdown mode, see Shutdown and Power-On-Reset (POR) for additional information. The PGA uses a standard serial peripheral interface (SPI). Both SPI Mode 0,0 and Mode 1,1 are supported. More information regarding serial communications, including daisy chaining can be found in Serial Interface Information.
BINARY GAIN (V/V) | TYPICAL –3-dB FREQUENCY (MHz) |
SLEW RATE-FALL (V/μs) |
SLEW RATE-RISE (V/μs) |
0.1% SETTLING TIME: 4 VPP (μs) |
0.01% SETTLING TIME: 4 VPP (μs) |
SCOPE GAIN (V/V) |
TYPICAL –3-dB FREQUENCY (MHz) |
SLEW RATE-FALL (V/μs) |
SLEW RATE-RISE (V/μs) |
0.1% SETTLING TIME: 4 VPP (μs) |
0.01% SETTLING TIME: 4 VPP (μs) |
|
---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 10 | 8 | 3 | 2 | 2.55 | 1 | 10 | 8 | 3 | 2 | 2.55 | |
2 | 3.8 | 9 | 6.4 | 2 | 2.6 | 2 | 3.8 | 9 | 6.4 | 2 | 2.6 | |
4 | 2 | 12.8 | 10.6 | 2 | 2.6 | 5 | 1.8 | 12.8 | 10.6 | 2 | 2.6 | |
8 | 1.8 | 12.8 | 10.6 | 2 | 2.6 | 10 | 1.8 | 12.8 | 10.6 | 2.2 | 2.6 | |
16 | 1.6 | 12.8 | 12.8 | 2.3 | 2.6 | 20 | 1.3 | 12.8 | 9.1 | 2.3 | 2.8 | |
32 | 1.8 | 12.8 | 13.3 | 2.3 | 3 | 50 | 0.9 | 9.1 | 7.1 | 2.4 | 3.8 | |
64 | 0.6 | 4 | 3.5 | 3 | 6 | 100 | 0.38 | 4 | 3.5 | 4.4 | 7 | |
128 | 0.35 | 2.5 | 2.5 | 4.8 | 8 | 200 | 0.23 | 2.3 | 2 | 6.9 | 10 |
MODE | CPOL | CPHA | CPOL DESCRIPTION | CPHA DESCRIPTION |
---|---|---|---|---|
0, 0 | 0 | 0(1) | Clock idles low | Data are read on the rising edge of clock. Data change on the falling edge of clock. |
1, 1 | 1 | 1(2) | Clock idles high | Data are read on the rising edge of clock. Data change on the falling edge of clock. |
The PGA uses a standard serial peripheral interface (SPI). Both SPI Mode 0,0 and Mode 1,1 are supported, as shown in Figure 56 and described in Table 2.
If there are not even-numbered increments of 16 clocks (that is, 16, 32, 64, and so forth) between CS going low (falling edge) and CS going high (rising edge), the device takes no action. This condition provides reliable serial communication. Furthermore, this condition also provides a way to quickly reset the SPI interface to a known starting condition for data synchronization. Transmitted data are latched internally on the rising edge of CS.
On the PGA116 and PGA117 devices, CS, DIN, and SCLK are Schmitt-triggered CMOS logic inputs. DIN has a weak internal pulldown to support daisy-chain communications on the PGA116 and PGA117 devices. DOUT is a CMOS logic output. When CS is high, the state of DOUT is high-impedance. When CS is low, DOUT is driven as illustrated in Figure 57.
On the PGA112 and PGA113 devices, there are digital output and digital input gates both internally connected to the DIO pin. DIN is an input-only gate and DOUT is a digital output that can give a 3-state output. The DIO pin has a weak 10-μA pulldown current source to prevent the pin from floating in systems with a high-impedance SPI DOUT line. When CS is high, the state of the internal DOUT gate is high-impedance. When CS is low, the state of DIO depends on the previous valid SPI communication; either DIO becomes an output to clock out data or it remains an input to receive data. This structure is shown in Figure 58.
To reduce the number of I/O port pins used on a microcontroller, the PGA116 and PGA117 support SPI daisy-chain communications with full read and write capability. A two-device daisy-chain configuration is shown in Figure 59, although any number of devices can be daisy-chained. The SPI daisy-chain communication uses a common SCLK and CS line for all devices in the daisy chain, rather than each device requiring a separate CS line. The daisy-chain mode of communication routes data serially through each device in the chain by using its respective DIN and DOUT pins as shown. Special commands are used (see Table 4) to ensure that data are written or read in the proper sequence. There is a special daisy-chain NOP command (No OPeration) which, when presented to the desired device in the daisy-chain, causes no changes in that respective device. Detailed timing diagrams for daisy-chain operation are shown in Figure 63 through Figure 65.
The PGA112 and PGA113 devices can be used as the last device in a daisy-chain as shown in Figure 60 if write-only communication is acceptable, because the PGA112 and PGA113 devices have no separate DOUT pin to connect back to the microcontroller DIN pin to read back data in this configuration.
The maximum SCLK frequency that can be used in daisy-chain operation is directly related to SCLK rise and fall times, DIN setup time, and DOUT propagation delay. Any number of two or more devices have the same limitations because it is the timing considerations between adjacent devices that limit the clock speed.
Figure 61 analyzes the maximum SCLK frequency for daisy-chain mode based on the circuit of Figure 59. A clock rise and fall time of 10 ns is assumed to allow for extra bus capacitance that could occur as a result of multiple devices in the daisy-chain.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | THREE-WIRE SPI COMMAND | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | READ | |
0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | G3 | G2 | G1 | G0 | CH3 | CH2 | CH1 | CH0 | WRITE | |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP WRITE | |
1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SDN_DIS WRITE | |
1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | SDN_EN WRITE |
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DAISY-CHAIN COMMAND | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP | |
1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SDN_DIS | |
1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | SDN_EN | |
0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | READ | |
0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | G3 | G2 | G1 | G0 | CH3 | CH2 | CH1 | CH0 | WRITE |
G3 | G2 | G1 | G0 | BINARY GAIN | SCOPE GAIN |
---|---|---|---|---|---|
0 | 0 | 0 | 0 | 1 | 1 |
0 | 0 | 0 | 1 | 2 | 2 |
0 | 0 | 1 | 0 | 4 | 5 |
0 | 0 | 1 | 1 | 8 | 10 |
0 | 1 | 0 | 0 | 16 | 20 |
0 | 1 | 0 | 1 | 32 | 50 |
0 | 1 | 1 | 0 | 64 | 100 |
0 | 1 | 1 | 1 | 128 | 200 |
CH3 | CH2 | CH1 | CH0 | PGA112, PGA113 | PGA116, PGA117 |
---|---|---|---|---|---|
0 | 0 | 0 | 0 | VCAL/CH0 | VCAL/CH0 |
0 | 0 | 0 | 1 | CH1 | CH1 |
0 | 0 | 1 | 0 | X(1) | CH2 |
0 | 0 | 1 | 1 | X | CH3 |
0 | 1 | 0 | 0 | X | CH4 |
0 | 1 | 0 | 1 | X | CH5 |
0 | 1 | 1 | 0 | X | CH6 |
0 | 1 | 1 | 1 | X | CH7 |
1 | 0 | 0 | 0 | X | CH8 |
1 | 0 | 0 | 1 | X | CH9 |
1 | 0 | 1 | 0 | X | X(1) |
1 | 0 | 1 | 1 | Factory Reserved | Factory Reserved |
1 | 1 | 0 | 0 | CAL1(2) | CAL1(2) |
1 | 1 | 0 | 1 | CAL2(3) | CAL2(3) |
1 | 1 | 1 | 0 | CAL3(4) | CAL3(4) |
1 | 1 | 1 | 1 | CAL4(5) | CAL4(5) |