SBOS729A October   2015  – March 2016 DRV425

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fluxgate Sensor Front-End
        1. 7.3.1.1 Fluxgate Sensor
        2. 7.3.1.2 Bandwidth
        3. 7.3.1.3 Differential Driver for the Internal Compensation Coil
        4. 7.3.1.4 Magnetic Field Range, Overrange Indicator, and Error Flag
      2. 7.3.2 Shunt-Sense Amplifier
      3. 7.3.3 Voltage Reference
      4. 7.3.4 Low-Power Operation of the DRV425
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Linear Position Sensing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Current Sensing in Busbars
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 Power-Supply Decoupling
    2. 9.2 Power-On Start-Up and Brownout
    3. 9.3 Power Dissipation
      1. 9.3.1 Thermal Pad
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power-Supply Recommendations

9.1 Power-Supply Decoupling

Decouple both VDD pins of the DRV425 with 1-µF, X7R-type ceramic capacitors to the adjacent GND pin as illustrated in Figure 76. For best performance, place both decoupling capacitors as close to the related power-supply pins as possible. Connect these capacitors to the power-supply source in a way that allows the current to flow through the pads of the decoupling capacitors.

9.2 Power-On Start-Up and Brownout

Power-on is detected when the supply voltage exceeds 2.4 V at the VDD pin. At this point, the DRV425 initiates the following start-up sequence:

  1. Digital logic starts up and waits for 26 μs for the supply to settle.
  2. The fluxgate sensor powers up.
  3. The compensation loop is active 70 μs after the supply voltage exceeds 2.4 V.

During this startup sequence, the DRV1 and DRV2 outputs are pulled low to prevent undesired signals on the compensation coil and the ERROR pin is asserted low.

The DRV425 tests for low supply voltages with a brownout voltage level of 2.4 V. Use a power-supply source capable of supporting large current pulses driven by the DRV425, and low-ESR bypass capacitors for a stable supply voltage in the system. A supply drop below 2.4 V that lasts longer than 20 μs generates a power-on reset; the device ignores shorter voltage drops. A voltage drop on the VDD pin to below 1.8 V immediately initiates a power-on reset. After the power supply returns to 2.4 V, the device initiates a start-up cycle.

9.3 Power Dissipation

The thermally-enhanced, PowerPAD, WQFN package reduces the thermal impedance from junction to case. This package has a downset lead frame that the die is mounted to. The lead frame has an exposed thermal pad (PowerPAD) on the underside of the package, and provides a good thermal path for heat dissipation.

The power dissipation on both linear outputs DRV1 and DRV2 is calculated with Equation 7:

Equation 7. PD(DRV) = IDRV × (VDRV – VSUPPLY)

where

  • IDRV = supply current as shown in Figure 59,
  • VDRV = voltage potential on the DRV1 or DRV2 output pin, and
  • VSUPPLY = voltage potential closer to VDRV: VDD or GND

9.3.1 Thermal Pad

Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but board layout greatly influences the overall heat dissipation. Technical details are described in application report PowerPad Thermally Enhanced Package, SLMA002, available for download at www.ti.com.