SBOS729A October   2015  – March 2016 DRV425

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fluxgate Sensor Front-End
        1. 7.3.1.1 Fluxgate Sensor
        2. 7.3.1.2 Bandwidth
        3. 7.3.1.3 Differential Driver for the Internal Compensation Coil
        4. 7.3.1.4 Magnetic Field Range, Overrange Indicator, and Error Flag
      2. 7.3.2 Shunt-Sense Amplifier
      3. 7.3.3 Voltage Reference
      4. 7.3.4 Low-Power Operation of the DRV425
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Linear Position Sensing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Current Sensing in Busbars
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 Power-Supply Decoupling
    2. 9.2 Power-On Start-Up and Brownout
    3. 9.3 Power Dissipation
      1. 9.3.1 Thermal Pad
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply voltage (VDD to GND) –0.3 6.5 V
Input voltage, except AINP and AINN pins(2) GND – 0.5 VDD + 0.5
Shunt-sense amplifier inputs (AINP and AINN pins)(3) GND – 6.0 VDD + 6.0
Current DRV1 and DRV2 pins (short-circuit current, IOS)(4) –300 300 mA
Shunt-sense amplifier input pins AINP and AINN –5 5
All remaining pins –25 25
Temperature Junction, TJ max –50 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited, except for the differential amplifier input pins.
(3) These inputs are not diode-clamped to the power-supply rails.
(4) Power-limited; observe maximum junction temperature.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage range (VDD to GND) 3.0 5.0 5.5 V
TA Specified ambient temperature range –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) DRV425 UNIT
RTJ (WQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 34.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 33.1 °C/W
RθJB Junction-to-board thermal resistance 11 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 11 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

All minimum and maximum specifications are at TA = 25°C, VDD = 3.0 V to 5.5 V, and IDRV1 = IDRV2 = 0 mA, unless otherwise noted. Typical values are at VDD = 5.0 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FLUXGATE SENSOR FRONT-END
Offset No magnetic field –8 ±2 8 µT
Offset drift No magnetic field ±5 nT/°C
G Gain Current at DRV1 and DRV2 outputs 12.2 mA/mT
Gain error ±0.04%
Gain drift Best-fit line method ±7 ppm/°C
Linearity error 0.1%
Hysteresis Magnetic field sweep from –10 mT to 10 mT 1.4 µT
Noise f = 0.1 Hz to 10 Hz 17 nTrms
Noise density f = 1 kHz 1.5 nT/√Hz
Compensation range –2 2 mT
Saturation trip level for the
ERROR pin(2) 		Open-loop, uncompensated field 1.6 mT
ERROR delay Open-loop at B > 1.6 mT 4 to 6 µs
BW Bandwidth BSEL = 0, RSHUNT = 22 Ω 32 kHz
BSEL = 1, RSHUNT = 22 Ω 47
IOS Short-circuit current VDD = 5 V 250 mA
VDD = 3.3 V 150
Common-mode output voltage at the DRV1 and DRV2 pins VREFOUT V
Compensation coil resistance 100 Ω
SHUNT-SENSE AMPLIFIER
VOO Output offset voltage VAINP = VAINN = VREFIN, VDD = 3.0 V –0.075 ±0.01 0.075 mV
Output offset voltage drift –2 ±0.4 2 µV/°C
CMRR Common-mode rejection ratio, RTO(1) VCM = –1 V to VDD + 1 V, VREFIN = VDD / 2 –250 ±50 250 µV/V
PSRRAMP Power-supply rejection ratio, RTO(1) VDD = 3.0 V to 5.5 V, VCM = VREFIN –50 ±4 50 µV/V
VICR Common-mode input voltage range –1 VDD + 1 V
zid Differential input impedance 16.5 20 23.5 kΩ
zic Common-mode input impedance 40 50 60 kΩ
Gnom Nominal gain VVOUT / (VAINP – VAINN) 4 V/V
EG Gain error –0.3% ±0.02% 0.3%
Gain error drift –5 ±1 5 ppm/°C
Linearity error 12 ppm
Voltage output swing from negative rail (OR pin trip level)(2) VDD = 5.5 V, IVOUT = 2.5 mA 48 85 mV
VDD = 3.0 V, IVOUT = 2.5 mA 56 100
Voltage output swing from positive rail (OR pin trip level)(2) VDD = 5.5 V, IVOUT = –2.5 mA VDD – 85 VDD – 48 mV
VDD = 3.0 V, IVOUT = –2.5 mA VDD – 100 VDD – 56
Signal overrange indication delay
(OR pin)(2) 		VIN = 1-V step 2.5 to 3.5 µs
IOS Short-circuit current VOUT connected to GND –18 mA
VOUT connected to VDD 20
BW–3dB Bandwidth 2 MHz
SR Slew rate 6.5 V/µs
tsa Settling time Large signal ΔV = ± 2 V to 1%, no external filter 0.9 µs
Small signal ΔV = ± 0.4 V to 0.01% 8
en Output voltage noise density f = 1 kHz, compensation loop disabled 170 nV/√Hz
VREFIN Input voltage range at pin REFIN Input voltage range at REFIN pin GND VDD V
VOLTAGE REFERENCE
VREFOUT Reference output voltage at the REFOUT pin RSEL[1:0] = 00, no load 2.45 2.5 2.55 V
RSEL[1:0] = 01, no load 1.6 1.65 1.7
RSEL[1:0] = 1x, no load 45 50 55 % of VDD
Reference output voltage drift RSEL[1:0] = 0x –50 ±10 50 ppm/°C
Voltage divider gain error drift RSEL[1:0] = 1x –50 ±10 50 ppm/°C
PSRRREF Power-supply rejection ratio RSEL[1:0] = 0x –300 ±15 300 µV/V
ΔVO(ΔIO) Load regulation RSEL[1:0] = 0x, load to GND or VDD,
ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C		 0.15 0.35 mV/mA
RSEL[1:0] = 1x, load to GND or VDD,
ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C		 0.3 0.8
IOS Short-circuit current REFOUT connected to VDD 20 mA
REFOUT connected to GND –18 mA
DIGITAL INPUTS/OUTPUTS (CMOS)
IIL Input leakage current 0.01 µA
VIH High-level input voltage TA = –40°C to +125°C 0.7 × VDD VDD + 0.3 V
VIL Low-level input voltage TA = –40°C to +125°C –0.3 0.3 × VDD V
VOH High-level output voltage Open-drain output Set by external pullup resistor V
VOL Low-level output voltage 4-mA sink current 0.3 V
POWER SUPPLY
IQ Quiescent current IDRV1/2 = 0 mA, 3.0 V ≤ VDD ≤ 3.6 V,
TA = –40°C to +125°C		 6 8 mA
IDRV1/2 = 0 mA, 4.5 V ≤ VDD ≤ 5.5 V,
TA = –40°C to +125°C		 7 10
VPOR Power-on reset threshold 2.4 V
(1) Parameter value is referred-to-output (RTO).
(2) See the Magnetic Field Range, Overrange Indicator, and Error Flag section for details on the behavior of the ERROR and OR outputs.

6.6 Typical Characteristics

at VDD = 5 V and TA = 25°C (unless otherwise noted)
DRV425 D001_SBOS704.gif
VDD = 5 V
Figure 1. Fluxgate Sensor Front-End Offset Histogram
DRV425 D003_SBOS704.gif
Figure 3. Fluxgate Sensor Front-End Offset vs
Supply Voltage
DRV425 D005_SBOS704.gif
Figure 5. Fluxgate Sensor Front-End Offset Drift Histogram
DRV425 D008_SBOS729.gif
Figure 7. Fluxgate Sensor Front-End Gain vs
Supply Voltage
DRV425 D057_SBOS729.gif
VDD = 5 V
Figure 9. Fluxgate Sensor Front-End Linearity Histogram
DRV425 D011_SBOS729.gif
Figure 11. Fluxgate Sensor Front-End Linearity vs Temperature
DRV425 D007_SBOS729.gif
VDD = 5 V
Figure 13. Fluxgate Sensor Saturation (ERROR Pin)
Trip Level Histogram
DRV425 D052_SBOS729.gif
Figure 15. Fluxgate Sensor Saturation (ERROR Pin) Trip Level vs Temperature
DRV425 D054_SBOS729.gif
Figure 17. Compensation Coil Resistance vs Temperature
DRV425 D016_SBOS704.gif
VDD = 3.3 V
Figure 19. Shunt-Sense Amplifier Output Offset Histogram
DRV425 D017_SBOS704.gif
Figure 21. Shunt-Sense Amplifier Output Offset vs Temperature
DRV425 D020_SBOS704.gif
Figure 23. Shunt-Sense Amplifier CMRR vs
Input Signal Frequency
DRV425 D022_SBOS704.gif
Figure 25. Shunt-Sense Amplifier PSRR vs
Ripple Frequency
DRV425 D024_SBOS704.gif
Figure 27. Shunt-Sense Amplifier AINP Input Impedance
vs Temperature
DRV425 D026_SBOS704.gif
Figure 29. Shunt-Sense Amplifier AINN Input Impedance
vs Temperature
DRV425 D055_SBOS729.gif
Including IFG, VDD = 3.3 V
Figure 31. Shunt-Sense Amplifier Gain Error Histogram
DRV425 D029_SBOS704.gif
Figure 33. Shunt-Sense Amplifier Gain vs
Input Signal Frequency
DRV425 D031_SBOS729.gif
Figure 35. OR Pin Trip Level vs Output Current
DRV425 D032_SBOS729.gif
Figure 37. OR Pin Trip Level vs Temperature
DRV425 D035_SBOS704.gif
Figure 39. Shunt-Sense Amplifier Output Short-Circuit Current vs Supply Voltage
DRV425 D012_SBOS729.gif
Rising edge
Figure 41. Shunt-Sense Amplifier Small-Signal
Settling Time
DRV425 D050_SBOS729.gif
Rising edge
Figure 43. Shunt-Sense Amplifier Large-Signal
Settling Time
DRV425 D036_SBOS729.gif
VDD = 5 V
Figure 45. Shunt-Sense Amplifier Overload Recovery Response
DRV425 D038_SBOS704.gif
Figure 47. Shunt-Sense Amplifier Output Voltage Noise Density vs Noise Frequency
DRV425 D058_SBOS729.gif
VREFOUT = 1.65 V
Figure 49. Reference Voltage Histogram
DRV425 D040_SBOS704.gif
Figure 51. Reference Voltage vs Temperature
DRV425 D041_SBOS704.gif
Figure 53. Reference Voltage Drift Histogram
DRV425 D045_SBOS704.gif
Figure 55. Reference Voltage Load Regulation Histogram
DRV425 D061_SBOS729.gif
Figure 57. Quiescent Current vs Supply Voltage
DRV425 D014_SBOS729.gif
Figure 59. Supply Current vs Magnetic Field
DRV425 D002_SBOS704.gif
VDD = 3.3 V
Figure 2. Fluxgate Sensor Front-End Offset Histogram
DRV425 D004_SBOS704.gif
Figure 4. Fluxgate Sensor Front-End Offset vs
Temperature
DRV425 D046_SBOS729.gif
VDD = 5 V
Figure 6. Fluxgate Sensor Front-End Gain Histogram
DRV425 D009_SBOS729.gif
Figure 8. Fluxgate Sensor Front-End Gain vs Temperature
DRV425 D010_SBOS729.gif
Figure 10. Fluxgate Sensor Front-End Linearity vs
Supply Voltage
DRV425 D006_SBOS704.gif
Figure 12. Fluxgate Sensor Front-End Noise Density vs Noise Frequency
DRV425 D013_SBOS729.gif
VDD = 3.3 V
Figure 14. Fluxgate Sensor Saturation (ERROR Pin)
Trip Level Histogram
DRV425 D053_SBOS729.gif
Figure 16. Compensation Coil Resistance Histogram
DRV425 D015_SBOS704.gif
VDD = 5 V
Figure 18. Shunt-Sense Amplifier Output Offset Histogram
DRV425 D018_SBOS704.gif
Figure 20. Shunt-Sense Amplifier Output Offset vs
Supply Voltage
DRV425 D019_SBOS704.gif
Figure 22. Shunt-Sense Amplifier CMRR Histogram
DRV425 D021_SBOS704.gif
Figure 24. Shunt-Sense Amplifier PSRR Histogram
DRV425 D023_SBOS704.gif
Figure 26. Shunt-Sense Amplifier AINP Input Impedance Histogram
DRV425 D025_SBOS704.gif
Figure 28. Shunt-Sense Amplifier AINN Input Impedance Histogram
DRV425 D027_SBOS704.gif
Including IFG, VDD = 5 V
Figure 30. Shunt-Sense Amplifier Gain Error Histogram
DRV425 D028_SBOS704.gif
Figure 32. Shunt-Sense Amplifier Gain Error vs
Temperature
DRV425 D030_SBOS704.gif
Figure 34. Shunt-Sense Amplifier Linearity Error vs
Supply Voltage
DRV425 D056_SBOS729.gif
Figure 36. OR Pin Trip Level vs Supply Voltage
DRV425 D033_SBOS704.gif
Figure 38. OR Pin Trip Delay vs Temperature
DRV425 D034_SBOS704.gif
Figure 40. Shunt-Sense Amplifier Output Short-Circuit Current vs Temperature
DRV425 D049_SBOS729.gif
Falling edge
Figure 42. Shunt-Sense Amplifier Small-Signal
Settling Time
DRV425 D051_SBOS729.gif
Falling edge
Figure 44. Shunt-Sense Amplifier Large-Signal
Settling Time
DRV425 D037_SBOS729.gif
VDD = 3.3 V
Figure 46. Shunt-Sense Amplifier Overload Recovery Response
DRV425 D039_SBOS729.gif
VREFOUT = 2.5 V
Figure 48. Reference Voltage Histogram
DRV425 D042_SBOS704.gif
Figure 50. Reference Voltage vs Supply Voltage
DRV425 D043_SBOS704.gif
Figure 52. Reference Voltage vs Reference Output Current
DRV425 D044_SBOS704.gif
Figure 54. Reference Voltage PSRR Histogram
DRV425 D060_SBOS729.gif
Figure 56. Reference Short-Circuit Current vs Temperature
DRV425 D048_SBOS729.gif
Figure 58. Quiescent Current vs Temperature
DRV425 D047_SBOS704.gif
Figure 60. Power-On Reset Threshold vs Temperature