SBOS854F March   2018  – June 2024 TMP1075

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics:TMP1075
    6. 6.6  Electrical Characteristics: TMP1075N
    7. 6.7  Timing Requirements:TMP1075
    8. 6.8  Timing Requirements: TMP1075N
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 I2C and SMBus Serial Interface
        1. 7.3.2.1  Bus Overview
        2. 7.3.2.2  Serial Bus Address
        3. 7.3.2.3  Pointer Register
          1. 7.3.2.3.1 Pointer Register Byte [reset = 00h]
        4. 7.3.2.4  Writing and Reading to the TMP1075
        5. 7.3.2.5  Operation Mode
          1. 7.3.2.5.1 Receiver Mode
          2. 7.3.2.5.2 Transmitter Mode
        6. 7.3.2.6  SMBus Alert Function
        7. 7.3.2.7  General Call- Reset Function
        8. 7.3.2.8  High-Speed Mode (HS)
        9. 7.3.2.9  Coexists in I3C Mixed Fast Mode
        10. 7.3.2.10 Time-Out Function
      3. 7.3.3 Timing Diagrams
      4. 7.3.4 Two-Wire Timing Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
      2. 7.4.2 One-Shot Mode (OS)
      3. 7.4.3 Continuous Conversion Mode (CC)
      4. 7.4.4 Thermostat Mode (TM)
        1. 7.4.4.1 Comparator Mode (TM = 0)
        2. 7.4.4.2 Interrupt Mode (TM = 1)
        3. 7.4.4.3 Polarity Mode (POL)
    5. 7.5 Register Map
      1. 7.5.1 Register Descriptions
        1. 7.5.1.1 Temperature Register (address = 00h) [default reset = 0000h]
        2. 7.5.1.2 Configuration Register (address = 01h) [default reset = 00FFh (60A0h TMP1075N)]
        3. 7.5.1.3 Low Limit Register (address = 02h) [default reset = 4B00h]
        4. 7.5.1.4 High Limit Register (address = 03h) [default reset = 5000h]
        5. 7.5.1.5 Device ID Register (address = 0Fh) [default reset = 7500]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Migrating From the xx75 Device Family
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 D Package 8-Pin SOIC Top View

Figure 5-3 DSG Package 8-Pin WSON Top View

Figure 5-2 DGK Package 8-Pin VSSOP Top View

  1. Pin 1 is determined by orienting the package marking as indicated in the diagram.
  2. Referred to as the TMP1075N orderable throughout the document.

Figure 5-4 DRL Package 6-Pin SOT563 Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME SOIC / VSSOP / WSON SOT563
A0 7 4 I Address select A0: Connect to GND, V+, SDA, or SCL
A1 6 — I Address select A1: Connect to GND, V+, SDA, or SCL
A2 5 — I Address select A2: Connect to GND or V+
ALERT 3 3 O Overtemperature alert; Open-drain output that requires a pullup resistor
GND 4 2 — Ground
SCL 2 1 I Serial clock
SDA 1 6 I/O Serial data. Open-drain output that requires a pullup resistor
V+ 8 5 I Supply voltage, 1.7 V to 5.5 V (TMP1075); 1.62 V to 3.6 V (TMP1075N)
(1) I = Input, O = Output, I/O = Input or Output