SBOSA51 December   2020 THS4567

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Differential TIA Mode, ICM loop enabled
    6. 6.6 Electrical Characteristics: FDA operation, ICM loop disabled
    7. 6.7 Typical Characteristics: (VS+) – (VS–) = 5 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Main Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Input Common-Mode Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Differential Transimpedance Amplifier Mode
      3. 7.4.3 Fully Differential Amplifier (FDA) Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noise Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure (THS4567 in TIA Mode)
        1. 8.2.2.1 OPA Mode Configuration
      3. 8.2.3 Application Curves
    3. 8.3 Differential TIA with 0-V Biased Photodiode
    4. 8.4 Differential AC Coupled TIA
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.6 Electrical Characteristics: FDA operation, ICM loop disabled

VS+ = 2.5 V, VS– = –2.5 V, VOCM = Open, VICM = Open, RF = 5 kΩ, Gain = 10 V/V, ICM loop disabled (ICM_EN = –2.5 V), RL = 1 kΩ and TA = 25°C. (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT (2) = 100 mVPP 43 MHz
LSBW Large-signal bandwidth VOUT (2) = 8 VPP 28 MHz
GBWP Gain bandwidth product 220 MHz
Slew rate VOUT = 8V Step, 20% ↔ 80% 500 V/µs
tR, tF Rise and fall time VOUT = 100 mVPP, 10% ↔ 90% 8 ns
0.1% settling time VOUT = 8V Step 65 ns
0.001% settling time 175
HD2 Second-order harmonic distortion f= 100 kHz, VOUT = 2 VPP –115 dBc
f= 100 kHz, VOUT = 8 VPP –105
HD3 Third-order harmonic distortion f= 100 kHz, VOUT = 2 VPP –118 dBc
f= 100 kHz, VOUT = 8 VPP –108
eN Input differential voltage noise f = 100 kHz 4.2 nV/√Hz
iN Input current noise, each input 10 fA/√Hz
ZOUT Closed-loop differential output impedance 0.2 Ω
DC PERFORMANCE
AOL Open-loop gain 104 117 dB
VOS Input-referred offset voltage VOS = (VIN+ – VIN–) –10 0.2 10 mV
ΔVOS/ΔTA Input-referred offset voltage drift TA = –40°C to +125°C 1 µV/°C
IBN, IBI Input bias current Noninverting and inverting inputs 20 pA
IOS Input offset current (IBN – IBI) ±20 pA
INPUT
Differential input resistance Effective shunt resistance between inputs 1 GΩ
Common-mode input resistance Effective shunt resistance to AC GND at each input 1
Differential input capacitance Effective shunt capacitance between inputs 0.6 pF
Common-mode input capacitance Effective shunt capacitance to AC GND at each input 0.9
CMRR Common-mode rejection ratio CMRR =  (ΔVCM/ΔVOS). Inputs shifted ±500 mV around midsupply 70 80 dB
CMIR+ Common-mode input high TA = 25°C, AOL > 90 dB VS+ – 1.85 VS+ – 1.6 V
TA = –40°C to +125°C, AOL > 90 dB VS+ – 1.65
CMIR– Common-mode input low TA = 25°C, AOL > 90 dB VS– + 0.2 VS– – 0.2 V
TA = –40°C to +125°C, AOL > 90 dB VS– – 0.1
OUTPUT
Output voltage range to either supply RL= 20 kΩ, TA = 25°C, input driven to  ±VS/Gain VS – 0.125 VS – 0.075 V
Output voltage range to either supply RL= 20 kΩ, TA = 25°C,
VOS shift < 150 µV from default offset		 VS – 0.175 VS – 0.125 V
Output voltage range to either supply RL= 20 kΩ, TA = –40°C to +125°C,
VOS shift < 150 µV from default offset		 VS – 0.175 V
Output voltage range to either supply RL= 1 kΩ, TA = 25°C,
VOS shift < 150 µV from default offset		 VS – 0.25 VS – 0.2 V
Output voltage range to either supply RL= 1 kΩ, TA = –40°C to +125°C,
VOS shift < 150 µV from default offset		 VS – 0.25 V
OUTPUT COMMON-MODE (VOCM) CONTROL
Output common-mode loop SSBW VOCM(3) pin driven ± 0.5 mV around midsupply 5 MHz
Output common-mode loop LSBW VOCM pin driven ± 0.5 V around midsupply 4.5 MHz
ΔVOUT
/ΔVOCM 		DC output balance (2) (3) VOCM = ±1 V 80 dB
ΔVOCM
/ΔVOCM		 Output common-mode gain (3) VOCM pin driven ±1 V around midsupply 0.99 1 1.01 V/V
Input DC bias current of VOCM pin VOCM pin driven to midsupply 100 nA
Input impedance of VOCM pin VOCM pin driven ± 0.5 mV around midsupply 200||1 kΩ || pF
VOCM input pin voltage offset from mid-supply (4) VOCM pin open –8 –2 4 mV
VOCM_OS Output common-mode voltage offset from midsupply VOCM pin open –30 ±2.5 30 mV
ΔVOCM_OS
/TA 		Output common-mode voltage offset drift TA = –40°C to +125°C, VOCM pin open –22 µV/°C
VOCM_OS Output common-mode voltage offset from midsupply VOCM pin driven to midsupply –25 ±1.5 25 mV
ΔVOCM_OS
/TA 		Output common-mode voltage offset drift TA = –40°C to +125°C, VOCM pin driven to midsupply –18 µV/°C
VOCM input headroom to VS+ ≤ ±10 mV shift from VOCM_OS 0.9 1 V
VOCM input headroom to VS+ TA = –40°C to +125°C, ≤ ±10 mV shift from VOCM_OS 1 V
VOCM input headroom from VS– ≤ ±10 mV shift from VOCM_OS 0.9 1 V
VOCM input headroom from VS– TA = –40°C to +125°C, ≤ ±10 mV shift from VOCM_OS 1 V
ΔVOCM_OS
/ΔVS+ 		Positive power-supply rejection ratio VOCM = 0 V (driven) 76 dB
ΔVOCM_OS
/ΔVS– 		Negative power-supply rejection ratio 80
POWER SUPPLY
IQ Quiescent current TA = 25°C 1.4 1.9 2.5 mA
IQ Quiescent current VICM loop enabled 1.5 2 2.7 mA
IQ Disabled quiescent current AMP_EN = VS– 10 28 40 µA
+PSRR Power-supply rejection ratio to VS+ VOCM is driven 70 94 dB
–PSRR Power-supply rejection ratio to VS– VOCM is driven 90 110 dB
POWER DOWN
VIH Enable voltage (Amplifier ON above this voltage) AMP_EN and ICM_EN VS+ – 0.7 VS+ – 0.5 V
VIL Disable voltage threshold (Amplifier OFF below this voltage) VS+ – 2 VS+ – 1.8
IIH Control pin HIGH Input bias current AMP_EN and ICM_EN driven to (VS+) – 0.25 V 3.5 7 µA
External pull-down current required to switch ON→OFF (1) 175 µA
IIL Control pin LOW Input bias current AMP_EN and ICM_EN driven to VS– –5 –1.1 µA
tAMP_ON Turn-ON time delay (Main amplifier) Time to VOUT stabilized within 1% of the final value 1.5 µs
tAMP_OFF Turn-OFF time delay (Main amplifier) Time to supply current ≤ 100 μA 0.9 µs
(1) Leaving the AMP_EN pin floating is not recommended. When using a pull-up resistor ensure that the necessary bias current can be supplied.
(2) VOUT is the differential output voltage, (VOUT– – VOUT+).
(3) VOCM refers to the voltage measured at pin 7. VOCM = [(VOUT+ + VOUT–)/2] refers to the average output voltage.
(4) The offset between the voltage measured at the VOCM pin and the midsupply voltage.