The device uses two sets of voltage supplies: input stage and output stage. The output-stage power supplies are decoupled from the input stage to limit the PGA849 output-swing voltage level protecting the ADC or downstream device against overdrive damage. The input-stage supplies, VS+ and VS–, are accessible using connector J13. The output-stage supplies, LVDD+ and LVSS–, are accessible using connector J14. Selectable jumpers J9 and J16 set the output-stage supply voltage level equal to the input-stage supplies (default), or to external voltages using connector J14.

The PGA849 incorporates features that simplify interfacing to a single-ended or pseudo-differential input ADC. The REF pin sets the reference point for the output voltage of the PGA849. The REF pin must be driven with a low-impedance source, and the evaluation board provides an optional buffer (U2) to drive the REF pin. Selectable jumper J1 provides options to set the REF pin voltage externally through connector J2, connects the REF to GND, or sets the REF to the PGA849 output-stage supplies (LVDD+ and LVSS–) mid-voltage value. The PGA849EVM allows access to the DA_IN– and DA_IN+ pins with optional capacitors C4 and C14. These capacitors are in parallel with the PGA849 output-stage difference amplifier internal resistors to implement noise filtering. Figure 3-1 displays a simplified block diagram of the PGA849EVM. For a full schematic of the PGA849EVM, see Figure 4-1.

Figure 2-1 PGA849EVM Simplified Schematic