SBVS066S December   2005  – November 2024 TPS74401

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable, Shutdown
      2. 6.3.2 Power-Good (VQFN Package Only)
      3. 6.3.3 Internal Current Limit
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
    5. 6.5 Programming
      1. 6.5.1 Programmable Soft-Start
      2. 6.5.2 Sequencing Requirements
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Output Noise
    2. 7.2 Typical Applications
      1. 7.2.1 Setting the TPS74401
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Using an Auxiliary Bias Rail
      3. 7.2.3 Without an Auxiliary Bias
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation
        2. 7.4.1.2 Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
      2. 8.1.2 Device Nomenclature
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Evaluation Modules
        2. 8.2.1.2 Spice Models
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Thermal Information

THERMAL METRIC(1) TPS744(2) UNIT
RGW (VQFN) RGW (VQFN)(3) RGR (VQFN) KTW (TO-263)
20 PINS 20 PINS 20 PINS 7 PINS
RθJA Junction-to-ambient thermal resistance 35.4 34.7 39.1 26.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.4 31 29.3 41.7 °C/W
RθJB Junction-to-board thermal resistance 14.7 13.5 10.2 12.5 °C/W
ψJT Junction-to-top characterization parameter 0.4 1.4 0.4 4.0 °C/W
ψJB Junction-to-board characterization parameter 14.8 13.5 10.1 7.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.9 3.6 2.0 0.3 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics the application note.
(2) Thermal data for the RGW, RGR, and KTW packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. RGW and RGR: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. - ii. KTW: The exposed pad is connected to the PCB ground layer through a 6x6 thermal via array. (b) Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, refer to the Thermal Considerations section.
(3) New Chip.