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  • TPS7A21 500-mA, Low-Noise, Low-IQ, High-PSRR LDO

    • SBVS398A December   2021  – September 2022 TPS7A21

      PRODUCTION DATA  

  • CONTENTS
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  • TPS7A21 500-mA, Low-Noise, Low-IQ, High-PSRR LDO
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Enable (EN)
      2. 7.3.2 Low Output Noise
      3. 7.3.3 Active Discharge
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Foldback Current Limit
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Overload Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Load Transient Response
      4. 8.1.4 Undervoltage Lockout (UVLO) Operation
      5. 8.1.5 Power Dissipation (PD)
      6. 8.1.6 Estimating Junction Temperature
      7. 8.1.7 Recommended Area For Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Device Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 DSBGA Mounting
        2. 8.4.1.2 DSBGA Light Sensitivity
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data
  11. IMPORTANT NOTICE
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DATA SHEET

TPS7A21 500-mA, Low-Noise, Low-IQ, High-PSRR LDO

1 Features

  • Very low IQ: 6.5 μA
  • Input voltage range: 2.0 V to 6.0 V
  • Output voltage range: 0.8 V to 5.5 V (50-mV steps)
  • High PSRR: 91 dB at 1 kHz
  • Low output voltage noise: 7.7 μVRMS
  • Low dropout:
    • 175 mV (maximum) at 500 mA (2.5-V VOUT)
  • Smart EN pulldown
  • Output voltage tolerance:
    • ±1.5% (line, load, and temperature)
  • Supports wide range of ceramic capacitors:
    • 1 µF to 200 µF
  • Operating junction temperature: –40°C to +125°C
  • Package:

    • 0.602-mm × 0.602-mm power DSBGA

2 Applications

  • Mobile phones and tablets
  • Wearables
  • IP cameras
  • Portable medical equipment
  • Smart meters and field transmitters
  • RF, PLL, VCO, and clock power supplies
  • Motor drives

3 Description

The TPS7A21 is an ultra-small, low-dropout (LDO) linear voltage regulator that can source 500 mA of output current. The device provides low noise, high PSRR, and excellent load and line transient performance to meet the requirements of RF and other sensitive analog circuits. Innovative design techniques result in low-noise performance without the addition of an external noise bypass capacitor. With the device low quiescent current, the TPS7A21 is a good choice for battery-powered systems. The 2.0-V to 6.0-V input voltage range and 0.8-V to 5.5-V output voltage range support a variety of system requirements. The internal precision reference circuit enables excellent accuracy; the maximum output voltage tolerance is 1.5% over load, line, and temperature variations.

An internal soft-start circuit helps control the inrush current, thus minimizing the input voltage drop during start up. The LDO is stable with small ceramic capacitors, allowing for a small overall solution size.

A smart enable input circuit with an internally controlled pulldown resistor keeps the LDO disabled even when the EN pin is unconnected and helps eliminate external components that are otherwise required to pull down the EN input.

Package Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
TPS7A21YWD (DSBGA, 4)0.602 mm × 0.602 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20211119-SS0I-MLRB-WXLG-KZ03CDPGJ8KG-low.gif Simplified Schematic

4 Revision History

Changes from Revision * (December 2021) to Revision A (September 2022)

  • Added line, load, and temperature to Output voltage tolerance bullet in Features sectionGo
  • Changed Supports wide range of ceramic capacitors bullet in Features sectionGo
  • Changed Applications sectionGo
  • Changed description of OUT pin in Pin Functions: DSBGA tableGo
  • Changed typical short-circuit current limit from 300 mA to 325 mA.Go
  • Changed typical value of smart enable pulldown resistor from 450 kΩ to 440 kΩ.Go
  • Changed Output Voltage Accuracy vs IOUT and IQ vs VIN figures in Typical Characteristics sectionGo
  • Deleted second IGND vs IOUT figure from Typical Characteristics sectionGo
  • Added discussion regarding sources with limited current drive capability to Smart Enable (EN) sectionGo
  • Changed correct value to nominal value Go
  • Added discussion that input voltage must be high enough to enable the active discharge to Active Discharge sectionGo
  • Added last sentence to Dropout Operation sectionGo
  • Changed Input voltage and Output current parameters in Design Parameters tableGo
  • Changed Detailed Design Procedure sectionGo
  • Added Device Nomenclature sectionGo

5 Pin Configuration and Functions

Figure 5-1 YWD Package,4-Pin DSBGA
Table 5-1 Pin Functions: DSBGA
PINI/ODESCRIPTION
DSBGANAME
A1INIInput voltage supply. For best transient response and to minimize input impedance, use the recommended value or larger capacitor from IN to GND, as listed in the Section 6.3 table. Place the input capacitor as close to the IN and GND pins of the device as possible.
A2OUTORegulated output voltage. Connect a low-equivalent series resistance (ESR) capacitor to this pin. For best transient response, use the nominal recommended value or larger capacitor from OUT to GND. An internal 150-Ω (typical) pulldown resistor prevents a charge from remaining on OUT when the regulator is in shutdown mode (VEN< VEN(LOW)).
B1ENIEnable input. A low voltage (VEN < VEN(LOW)) on this pin turns the regulator off and discharges the output pin to GND through an internal 150-Ω pulldown resistor. A high voltage (VEN > VEN(HI)) on this pin enables the regulator output. This pin has an internal 450-kΩ pulldown resistor to hold the regulator off by default. When VEN > VEN(HI), the 450-kΩ pulldown resistor is disconnected to reduce input current.
B2GND—Common ground.

6 Specifications

6.1 Absolute Maximum Ratings

ratings apply over operating free-air temperature range (unless otherwise noted)(1)(3)
MIN MAX UNIT
VIN Input voltage –0.3 6.5 V
VOUT Output voltage –0.3 See(2) V
VEN Enable input voltage –0.3 6.5 V
Maximum output current(4) Internally limited A
TJ Operating junction temperature -40 150 °C
Tstg Storage temperature –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Absolute maximum VOUT is the lesser of VIN + 0.3 V, or 6.5 V.
(3) All voltages are with respect to the GND pin.
(4) Internal thermal shutdown circuitry helps protect the device from permanent damage.

 
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