• Menu
  • Product
  • Email
  • PDF
  • Order now

  • CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs

    • SCAS862G November   2008  – July 2016 CDCE62005

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 SPI Bus Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
      1. 8.2.1 Interface and Control Block
      2. 8.2.2 Input Block
      3. 8.2.3 Output Block
      4. 8.2.4 Clock Divider Module 0-4
      5. 8.2.5 Synthesizer Block
      6. 8.2.6 Computing The Output Frequency
    3. 8.3 Feature Description
      1. 8.3.1  Phase Noise Analysis
      2. 8.3.2  Output To Output Isolation
      3. 8.3.3  Device Control
      4. 8.3.4  External Control Pins
      5. 8.3.5  Input Block
        1. 8.3.5.1  Universal Input Buffers (UIB)
        2. 8.3.5.2  LVDS Fail Safe Mode
        3. 8.3.5.3  Smart Multiplexer Controls
        4. 8.3.5.4  Smart Multiplexer Auto Mode
        5. 8.3.5.5  Smart Multiplexer Dividers
        6. 8.3.5.6  Output Block
        7. 8.3.5.7  Output Multiplexer Control
        8. 8.3.5.8  Output Buffer Control
        9. 8.3.5.9  Output Buffer Control - LVCMOS Configurations
        10. 8.3.5.10 Output Dividers
        11. 8.3.5.11 Digital Phase Adjust
        12. 8.3.5.12 Phase Adjust Example
        13. 8.3.5.13 Valid Register Settings for Digital Phase Adjust Blocks
        14. 8.3.5.14 Output Synchronization
        15. 8.3.5.15 Auxiliary Output
        16. 8.3.5.16 Synthesizer Block
        17. 8.3.5.17 Input Divider
        18. 8.3.5.18 Feedback and Feedback Bypass Divider
          1. 8.3.5.18.1 VCO Select
          2. 8.3.5.18.2 Prescaler
          3. 8.3.5.18.3 Charge Pump Current Settings
          4. 8.3.5.18.4 Loop Filter
        19. 8.3.5.19 Internal Loop Filter Component Configuration
        20. 8.3.5.20 External Loop Filter Component Configuration
      6. 8.3.6  Digital Lock Detect
      7. 8.3.7  Crystal Input Interference
      8. 8.3.8  VCO Calibration
      9. 8.3.9  Startup Time Estimation
      10. 8.3.10 Analog Lock Detect
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fan-Out Buffer
      2. 8.4.2 Clock Generator
      3. 8.4.3 Jitter Cleaner - Mixed Mode
        1. 8.4.3.1 Clocking ADCs with the CDCE62005
        2. 8.4.3.2 CDCE62005 SERDES Startup Mode
    5. 8.5 Programming
      1. 8.5.1 Interface and Control Block
        1. 8.5.1.1 Serial Peripheral Interface (SPI)
        2. 8.5.1.2 CDCE62005 SPI Command Structure
        3. 8.5.1.3 SPI Interface Master
        4. 8.5.1.4 SPI Consecutive Read/Write Cycles to the CDCE62005
        5. 8.5.1.5 Writing to the CDCE62005
        6. 8.5.1.6 Reading from the CDCE62005
        7. 8.5.1.7 Writing to EEPROM
      2. 8.5.2 Device Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers: Register 0 Address 0x00
      2. 8.6.2 Device Registers: Register 1 Address 0x01
      3. 8.6.3 Device Registers: Register 2 Address 0x02
      4. 8.6.4 Device Registers: Register 3 Address 0x03
      5. 8.6.5 Device Registers: Register 4 Address 0x04
      6. 8.6.6 Device Registers: Register 5 Address 0x05
      7. 8.6.7 Device Registers: Register 6 Address 0x06
      8. 8.6.8 Device Registers: Register 7 Address 0x07
      9. 8.6.9 Device Registers: Register 8 Address 0x08
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Frequency Synthesizer
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Documentation Support
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs

1 Features

  • Superior Performance:
    • Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
    • Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
  • Flexible Frequency Planning:
    • 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
    • Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
    • Output Frequency up to 1.5 GHz in Fan-Out Mode
    • Independent Coarse Skew Control on all Outputs
  • High Flexibility:
    • Integrated EEPROM Determines Device Configuration at Power-up
    • Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
  • 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
  • –40°C to +85°C Temperature Range

2 Applications

  • Wireless Infrastructure
  • Switches and Routers
  • Medical Electronics
  • Military and Aerospace
  • Industrial

3 Description

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).

The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.

The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCE62005 VQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Application Example

CDCE62005 app_exp_cas862.gif

4 Revision History

Changes from F Revision (January 2015) to G Revision

  • Removed minimum and maximum values and added typical value to on-chip load capacitance in Electrical Characteristics Go

Changes from E Revision (July 2014) to F Revision

  • Added Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth), FC = 100 MHz in Features sectionGo
  • Added Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth), FC = 100 MHz in Features sectionGo

Changes from D Revision (April 2011) to E Revision

  • Changed Added, updated, or revised the following sections: Features; Application and Implementation; Power Supply Recommendations ; Layout ; Device and Documentation Support ; Mechanical, Packaging, and Ordering Information Go
  • Changed Bit Name from LOCKW(3) to LOCKW(2)Go
  • Changed Bit Name from LOCKW(2) to LOCKW(1)Go
  • Changed Bit Name from LOCKW(1) to LOCKW(0)Go
  • Changed REGISTER.BIT from 5.26 to 5.25, from 5.25 to 5.24, from 5.24 to 5.23, from 5.23 to 5.22. Go

Changes from C Revision (February, 2010) to D Revision

  • Changed 0 to 1 in SPI_LE descriptionGo
  • Changed last sentence in Description column of Pin 46 and Pin 2Go
  • Changed Outputs to Output 1 in PLVCMOS Test Conditions, changed PD to Power_Down in LVCMOS INPUT MODE, and deleted (LVCMOS signals) from Input capacitance in Electrical CharacteristicsGo
  • Changed TIMING REQUIREMENTS tableGo
  • Added 1 row to TIMING Requirements table - Input Clock Slew Rate...Go
  • Added SPI CONTROL INTERFACE TIMING sectionGo
  • Changed Functional Block Diagrams Go
  • Changed pin names in Figure 11Go
  • Changed Feedback Divider value in Figure 15Go
  • Changed are 25°C to (nominal conditions) in Table 3Go
  • Changed Poer Down state SPI Port status from ON to OFF in Table 4Go
  • Changed Figure 18 Go
  • Changed Table 5 Go
  • Added note to Table 7Go
  • Changed AUXSEL from X to 0 in Table 7Go
  • Added note to Table 21Go
  • Added new sections Crystal Input Interface, VCO Calibration, and Startup Time Estimation.Go
  • Changed Serial Peripheral Interface (SPI) sectionGo
  • Changed Table 6 to Table 38 in Writing to EEPROM sectionGo
  • Changed RAM bit 1 and RAM bit 2 in Table 43Go
  • Added note and changed Smart MUX description in Table 45Go
  • Changed 1 to 0 in rows PRINVBB and SECINVB6 in the description columnGo
  • Changed RAM bit 22 from 0 to 1 and changed RAM bit 24 from 0 to 1 in Table 47Go
  • Changed Table 48 Go

Changes from B Revision (July, 2009) to C Revision

  • Deleted LVCMOS INPUT MODE (AUX_IN) section from Electrical Characteristics tableGo

5 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
CDCE62005 po_cas862.gif

Pin Functions(1)

PIN TYPE DESCRIPTION
NAME NO,
VCC_OUT 8, 11, 18, 21,
26, 29, 32		 Power 3.3-V Supply for the Output Buffers and Output Dividers
VCC_AUXOUT 15 Power 3.3-V to Power the AUX_OUT circuitry
VCC1_PLL 5 A. Power 3.3-V PLL Supply Voltage for the PLL circuitry. (Filter Required)
VCC2_PLL 39, 42 A. Power 3.3-V PLL Supply Voltage for the PLL circuitry. (Filter Required)
VCC_VCO 34, 35 A. Power 3.3-V VCO Input Buffer and Circuitry Supply Voltage. (Filter Required)
VCC_IN_PRI 47 A. Power 3.3-V References Input Buffer and Circuitry Supply Voltage.
VCC_IN_SEC 1 A. Power 3.3-V References Input Buffer and Circuitry Supply Voltage.
VCC_AUXIN 44 A. Power 3.3-V Crystal Oscillator Input Circuitry.
GND_VCO 36 Ground Ground that connects to VCO Ground. (VCO_GND is shorted to GND)
GND PAD Ground Ground is on Thermal PAD. See Layout recommendation
SPI_MISO 22 O 3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial Data Output to the SPI bus interface
SPI_LE 25 I LVCMOS input, control Latch Enable for Serial Programmable Interface (SPI), with Hysteresis in SPI Mode. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level 1. The SPI_LE status also impacts whether the device loads the EEPROM into the device registers at power up. SPI_LE has to be logic 1 before the Power_Down pin toggles low-to-high in order for the EEPROM to load properly.
SPI_CLK 24 I LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level 1.
SPI_MOSI 23 I LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62005 for the SPI bus interface. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level 1.
TEST_MODE 33 I This pin should be tied high or left unconnected.
REF_SEL 31 I If Auto Reference Select Mode is OFF this Pin acts as External Input Reference Select Pin;
The REF_SEL signal selects one of the two input clocks:
REF_SEL [1]: PRI_REF is selected; REF_SEL [0]: SEC_REF is selected;
The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level 1. If Auto Reference Select Mode in ON (for example, EECLKSEL bit -- Register 5 Bit 5 -- is 1 ), then REF_SEL pin input setting is ignored.
Power_Down 12 I Active Low. Power down mode can be activated via this pin. See Table 4 for more details. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level 1. SPI_LE has to be HIGH in order for the rising edge of Power_Down signal to load the EEPROM.
SYNC 14 I Active Low. Sync mode can be activated via this pin. See Table 4 for more details. The input has an internal 150-kΩ, pull-up resistor if left unconnected it will default to logic level 1.
AUX IN 43 I Auxiliary Input is a single ended input including an on-board oscillator circuit so that a crystal may be connected.
AUX OUT 13 O Auxiliary Output LVCMOS level that can be programmed via SPI interface to be driven by Output 2 or Output 3.
PRI_REF+ 45 I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference Clock.
PRI_REF– 46 I Universal Input Buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In case of LVCMOS input on PRI_REF+, connect this pin through 1-kΩ resistor to GND.
SEC_REF+ 3 I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary Reference Clock.
SEC_REF– 2 I Universal Input Buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. In case of LVCMOS input on SEC_REF+, connect this pin through 1-kΩ resistor to GND.
TESTOUTA 30 Analog Reserved. Pull Down to GND Via a 1-kΩ Resistor.
REG_CAP1 4 Analog Capacitor for the internal Regulator. Connect to a 10-µF Capacitor (X5R or X7R)
REG_CAP2 38 Analog Capacitor for the internal Regulator. Connect to a 10-µF Capacitor (X5R or X7R)
VBB 48 Analog Capacitor for the internal termination Voltage. Connect to a 1-µF Capacitor (X5R or X7R)
EXT_LFP 40 Analog External Loop Filter Input Positive
EXT_LFN 41 Analog External Loop Filter Input Negative.
PLL_LOCK 37 O Output that indicates PLL Lock Status. See Figure 31.
U0P:U0N
U1P:U1N
U2P:U2N
U3P:U3N
U4P:U4N		 27, 28
19, 20
16,17
9, 10
6, 7		 O The Main outputs of CDCE62005 are user definable and can be any combination of up to 5 LVPECL outputs, 5 LVDS outputs or up to 10 LVCMOS outputs. The outputs are selectable via SPI interface. The power-up setting is EEPROM configurable.
(1) Note: The internal memory (EEPROM and RAM) are sourced from various power pins. All VCC connections must be powered for proper functionality of the device.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale