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CDCE62005

ACTIVE

5/10 outputs clock generator/jitter cleaner with integrated dual VCO

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Data sheet

CDCE62005

ACTIVE
Data sheet Order now

Product details

Function Clock generator Number of outputs 5 Output frequency (max) (MHz) 1175 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
Function Clock generator Number of outputs 5 Output frequency (max) (MHz) 1175 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
VQFN (RGZ) 48 49 mm² 7 x 7
  • Superior Performance:
    • Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
    • Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
  • Flexible Frequency Planning:
    • 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
    • Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
    • Output Frequency up to 1.5 GHz in Fan-Out Mode
    • Independent Coarse Skew Control on all Outputs
  • High Flexibility:
    • Integrated EEPROM Determines Device Configuration at Power-up
    • Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
  • 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
  • –40°C to +85°C Temperature Range
  • Superior Performance:
    • Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
    • Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
  • Flexible Frequency Planning:
    • 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
    • Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
    • Output Frequency up to 1.5 GHz in Fan-Out Mode
    • Independent Coarse Skew Control on all Outputs
  • High Flexibility:
    • Integrated EEPROM Determines Device Configuration at Power-up
    • Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
  • 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
  • –40°C to +85°C Temperature Range

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).

The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.

The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).

The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.

The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
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Technical documentation

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Type Title Date
* Data sheet CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs datasheet (Rev. G) PDF | HTML 23 May 2016
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
User guide TSW6011EVM Quick Start Guide (Rev. D) 17 Aug 2016
Application note Clocking Design Guidelines: Unused Pins 19 Nov 2015
Application note Effects of Clock Spur on High Speed DAC Performance (Rev. A) 18 May 2015
Application note Effects of Clock Noise on High Speed DAC Performance 08 Nov 2012
Application note Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005 11 Aug 2011
Application note CDCE62005 Application Report 21 Nov 2008
Application note LAN & WAN clock generation and muxing using the CDCE62005 19 Nov 2008
User guide Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz 11 Nov 2008
Application note CDCE62005 Phase Noise and Jitter Cleaning Performance 05 Sep 2008
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008

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