SCDS404B March   2021  – November 2022 TMUX7411F , TMUX7412F , TMUX7413F

PRODMIX  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Electrical Characteristics: Global
    6. 7.6  ±15 V Dual Supply: Electrical Characteristics
    7. 7.7  ±20 V Dual Supply: Electrical Characteristics
    8. 7.8  12 V Single Supply: Electrical Characteristics
    9. 7.9  36 V Single Supply: Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Turn-On and Turn-Off Time
    3. 8.3  Off-Leakage Current
    4. 8.4  On-Leakage Current
    5. 8.5  Input and Output Leakage Current Under Overvoltage Fault
    6. 8.6  Fault Response Time
    7. 8.7  Fault Recovery Time
    8. 8.8  Fault Flag Response Time
    9. 8.9  Fault Flag Recovery Time
    10. 8.10 Charge Injection
    11. 8.11 Off Isolation
    12. 8.12 Inter-Channel Crosstalk
    13. 8.13 Bandwidth
    14. 8.14 THD + Noise
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Flat ON-Resistance
      2. 9.3.2 Protection Features
        1. 9.3.2.1 Input Voltage Tolerance
        2. 9.3.2.2 Powered-Off Protection
        3. 9.3.2.3 Fail-Safe Logic
        4. 9.3.2.4 Overvoltage Protection and Detection
        5. 9.3.2.5 ESD Protection
        6. 9.3.2.6 Latch-Up Immunity
        7. 9.3.2.7 EMC Protection
      3. 9.3.3 Overvoltage Fault Flags
      4. 9.3.4 Bidirectional Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Fault Mode
      3. 9.4.3 Truth Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Description

The TMUX7411F, TMUX7412F, and TMUX7413F are complementary metal-oxide semiconductor (CMOS) analog switches in 1:1 (SPST), 4-channel configurations. The devices work well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The overvoltage protection is available in powered and powered-off conditions, making the TMUX741xF devices suitable for applications where power supply sequencing cannot be precisely controlled.

The devices block fault voltages up to +60 V or
−60 V relative to ground in powered and powered-off conditions. When no power supplies are present, the switch channels remain in the OFF state regardless of the switch input conditions, and any control signal present on the logic pins is ignored. If the signal path input voltage on any Sx pin exceeds the supply voltage (VDD or VSS) by a threshold voltage (VT), the channel turns OFF and the Sx pin becomes high impedance. The drain pin (Dx) of a selected channel under a fault condition is floating. The TMUX741xF devices provide an active-low interrupt flag (FF) to indicate if any of the source inputs are experiencing a fault condition to help system diagnostics.

Package Information(1)(3)
PART NUMBERPACKAGEBODY SIZE (NOM)
TMUX7411F
TMUX7412F
TMUX7413F
PW (TSSOP, 16) (2)5.00 mm × 4.40 mm
RRP (WQFN, 16)4.00 mm × 4.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
Preview package.
GUID-EB092CDF-EE85-41D5-9DA3-DB2708D39558-low.gif Functional Block Diagram