In the past, existing level-shifter designs in the market were designed for general level-shifting applications. This posed difficulties for designers confirming if existing designs will work for high performance timing-sensitive interfaces with more complex requirements, such as RGMII. Examples of existing designs from TI includes the AXC (SN74AXC8T245) and the AVC families (SN74AVC8T245). However, the data sheets do not define the timing budget across process variations, voltages and temperature corners.

TI has developed a new TXV level shifter family, well tested and defined for strict timing budget interfaces across process variations, voltages and temperature corners to support such high performance requirements.

Within the TXV family, TXV0108 / TXV0108-Q1 (direction-controlled) have been intentionally made pin-to-pin compatible with the existing AXC and AVC families for systems using AXC / AVC for uni-directional applications.

The TXV0106 / TXV0106-Q1 (fixed-direction) shown in Figure 1-3 is an alternative, offering lower pin count which enables board space and cost savings.

As shown, TXV010x can be used to level-shift RGMII signals from MAC to PHY or PHY to MAC. It is recommended that the transmitter clock and data signals are on the same device, as well as the receiver clock and data signals. This is due to a small difference as low as 500 ps in skew (propagation delay between the output channels) may violate the requirement, with the possibility of data errors within the RGMII interfaces.