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TXV0108

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Dual-supply direction-controlled eight-channel voltage translator

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Data sheet

TXV0108

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Product details

Technology family AVC Applications GPIO, JTAG, SPI, UART Bits (#) 8 High input voltage (min) (V) 1.08 High input voltage (max) (V) 3.6 Vout (min) (V) 1.65 Vout (max) (V) 3.63 Data rate (max) (Mbps) 0.25 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AVC Applications GPIO, JTAG, SPI, UART Bits (#) 8 High input voltage (min) (V) 1.08 High input voltage (max) (V) 3.6 Vout (min) (V) 1.65 Vout (max) (V) 3.63 Data rate (max) (Mbps) 0.25 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State Rating Catalog Operating temperature range (°C) -40 to 125
VQFN (RGY) 24 19.25 mm² 5.5 x 3.5
  • Configurable design allows each port to operate with a power supply range from 1.14V to 3.6V
  • Supports up to 500Mbps for 1.65V to 3.6V
  • Meets RGMII 2.0 timing specifications:
    • < 750ps rise and fall time
    • < ± 5 % duty cycle distortion
    • < ± 400 ps channel to channel skew
    • Up to 250Mbps/Channel

  • Integrated 10 Ω damping output resistor to minimize signal reflections

  • High drive strength (up to 12mA at 3.6V)

  • Fully configurable symmetric dual-rail design
  • Optimal signal integrity performance with 390ps peak-to-peak jitter for 1.8V to 3.3V
  • Features VCC isolation and VCC disconnect
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 2000V Human-Body Model
    • 1000V Charged-Device Model
  • Low power consumption:
    • 10µA maximum (25°C)
    • 20µA maximum (–40°C to 125°C)
  • Operating temperature from –40°C to +125°C
  • Pin compatible with SN74AVC8T245 (VQFN)
  • Configurable design allows each port to operate with a power supply range from 1.14V to 3.6V
  • Supports up to 500Mbps for 1.65V to 3.6V
  • Meets RGMII 2.0 timing specifications:
    • < 750ps rise and fall time
    • < ± 5 % duty cycle distortion
    • < ± 400 ps channel to channel skew
    • Up to 250Mbps/Channel

  • Integrated 10 Ω damping output resistor to minimize signal reflections

  • High drive strength (up to 12mA at 3.6V)

  • Fully configurable symmetric dual-rail design
  • Optimal signal integrity performance with 390ps peak-to-peak jitter for 1.8V to 3.3V
  • Features VCC isolation and VCC disconnect
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 2000V Human-Body Model
    • 1000V Charged-Device Model
  • Low power consumption:
    • 10µA maximum (25°C)
    • 20µA maximum (–40°C to 125°C)
  • Operating temperature from –40°C to +125°C
  • Pin compatible with SN74AVC8T245 (VQFN)

The TXV0108 is an 8-bit, dual-supply direction controlled low-skew, low-jitter voltage translation device. This device can be used for redriving, voltage translation, and power isolation when implementing skew sensitive interface, such as RGMII between Ethernet MAC and PHY devices. The Ax I/O pins and control pins (DIR, OE) are referenced to VCCA logic levels, and Bx I/O pins are referenced to VCCB logic levels. This device has improved channel-to-channel skew, duty cycle distortion and symmetric rise and fall time for applications requiring strict timing conditions.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC supply is at or near 0V both ports will switch to a high-impedance state. This feature enables power isolation for communications across multiple MACs and PHYs, and is beneficial in situations where MACs and PHYs are powered up asynchronously preventing current backflow between devices.

A High on DIR allows data transmission from A to B while a Low on DIR allows data transmission from B to A when OE is set to Low. When OE is set to High, both Ax and Bx pins will be forced into a high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.

The TXV0108 is an 8-bit, dual-supply direction controlled low-skew, low-jitter voltage translation device. This device can be used for redriving, voltage translation, and power isolation when implementing skew sensitive interface, such as RGMII between Ethernet MAC and PHY devices. The Ax I/O pins and control pins (DIR, OE) are referenced to VCCA logic levels, and Bx I/O pins are referenced to VCCB logic levels. This device has improved channel-to-channel skew, duty cycle distortion and symmetric rise and fall time for applications requiring strict timing conditions.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC supply is at or near 0V both ports will switch to a high-impedance state. This feature enables power isolation for communications across multiple MACs and PHYs, and is beneficial in situations where MACs and PHYs are powered up asynchronously preventing current backflow between devices.

A High on DIR allows data transmission from A to B while a Low on DIR allows data transmission from B to A when OE is set to Low. When OE is set to High, both Ax and Bx pins will be forced into a high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.
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* Data sheet TXV0108 8-Bit Direction Controlled Low-Skew, Low-Jitter Voltage Translator or Buffer datasheet (Rev. A) PDF | HTML 12 Apr 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 14 May 2024
Application brief Enabling AI Accelerators with Voltage Level Translation PDF | HTML 01 May 2024
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
EVM User's guide TXV010xEVM Evaluation Module User's Guide PDF | HTML 05 Feb 2024
Application note Overcoming Design Challenges - Implementing High Performance Interfaces PDF | HTML 12 Dec 2023
Application brief Supporting Time and Skew Sensitive Interfaces with TI's TXV Level-Shifter PDF | HTML 27 Oct 2023
Application brief Enabling Industrial and Automotive Ethernet RGMII Interfaces with Voltage Transl PDF | HTML 02 Aug 2023

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