SCEU026 February   2024 SN74AVC8T245 , SN74AVC8T245-Q1 , SN74AXC8T245 , SN74AXC8T245-Q1 , SN74LVC8T245 , SN74LVC8T245-Q1 , SN74LXC8T245 , SN74LXC8T245-Q1 , TXV0106 , TXV0106-Q1 , TXV0108 , TXV0108-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Features
    2. 2.2 Hardware Description
      1. 2.2.1 Headers
      2. 2.2.2 Bypass Capacitors
      3. 2.2.3 Pull-up and Pull-down Resistors and Capacitive Loading
      4. 2.2.4 SMA Connectors
      5. 2.2.5 Set-up and Measurements
  9. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1.     Trademarks

Set-up and Measurements

The TXV devices are optimized for low skew applications such as RGMII interface between MAC and PHY. The EVMs have been optimized with options to measure skew. For skew measurements, the default state of the board with the SMA connectors populated can be used corresponding to the shortest PCB traces ready to be tested, For example, A3 and A4 as inputs for TXV0106-EVM and A1 and A8 as inputs for TXV0108-EVM ready to be tested.

Figure 4-4 shows typical rise / fall time, output skew and duty cycle distortion (DCD) measurements from the TXV0108-EVM (with the TXV0108 device). C1 (ch A1) and C2 (ch A8) are both inputs while C3 (ch B1) and C4 (ch B8) are the corresponding outputs respectively.

The scope shot highlights typical RGMII application with timing budget for rise and fall times <750ps (C4 as B8 output), output skew (C4, C3 as B8, B1 outputs) <400ps, DCD (C4 as B8 output) <5% of 50% and propagation delay tPD (C2, C4 as A8 input, B8 output) < 2ns for 1.8V to 3.3V at 125MHz with no load populated at the CLB_outputs.

GUID-20230622-SS0I-LJFD-2GR9-J47R2F5X6DXQ-low.svgGUID-20230721-SS0I-X9N7-M8QQ-6JBWKF4BCMWR-low.svgFigure 2-3 TXV0108-EVM with TXV0108RGY, 1.8V to 3.3V Translation

The signals are generated from two signal generator ports as shown in Figure 4-4 using short high-speed cables, connected to the edge-mounted SMA_A_1 and SMA_A_8 connectors and terminated at the 50-Ω termination resistors for the data inputs A1 & A8.

The corresponding input headers JA_1 & JA_8 are used to probe the input signals using active probes. The corresponding output headers JB_1 & JB_8 are used to probe the output signals using active probes (note that probes can add additional capacitance). CLB gives the option to include additional capacitive load conditions for further evaluations.

For B-to-A Translation:

  • Pull DIR low to GND.
  • Make sure the 50-Ω termination resistors on Rta_1 & Rta_8 are depopulated.
  • Make sure the 50-Ω termination resistors for Rtb_1 & Rtb_8 are populated.
  • Connect the input signal to SMA_B_1 & SMA_B_8.
  • Measure the outputs at JA_1 & JA_8.
  • Use CLA for additional capacitive loading.