SCEU031B August   2024  – October 2024 TPLD801

PRODUCTION DATA  

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Functional Blocks
      1. 2.1.1 Test Points
      2. 2.1.2 Programmer Header Block (P1)
      3. 2.1.3 External Connection Header Block
      4. 2.1.4 GPI Protection Block
      5. 2.1.5 DRL Socket
      6. 2.1.6 SW or LED Testing Blocks
      7. 2.1.7 GPI Switch Testing Block
  9. 3Software
    1. 3.1 Using the TPLD801-DRL-EVM
      1. 3.1.1 Equipment Needed for Programming
      2. 3.1.2 Installing Software
    2. 3.2 Configuring a TPLD Device
      1. 3.2.1 TPLD801-DRL-EVM Setup for Programming
      2. 3.2.2 Inserting a TPLD801DRL into the DRL Socket
      3. 3.2.3 Connecting the TPLD801-DRL-EVM to a TPLD-PROGRAM Board
      4. 3.2.4 Temporarily Configuring a TPLD Device
      5. 3.2.5 Permanently Programming a TPLD Device
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
      1. 4.2.1 PCB Overview
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Revision History

2.1.3 External Connection Header Block

The P2 header block is intended to be used to interface the TPLD801-DRL-EVM with an external system. Using the guide printed on the EVM silkscreen, the TPLD pins can be interfaced with an external system to allow for prototyping and testing in customer systems. When supplying power to the TPLD using the P2 header block, SW8 needs to be in the OFF position and a shunt placed on J1, connecting the external VCC supply from P2 (VCC_EXT) to the VCC net of the EVM. TI recommends not connecting the board to an external system and to the TPLD-PROGRAM at the same time to avoid the risk of damage to the TPLD-PROGRAM and the external system.

TPLD801-DRL-EVM P2 and J1 HeadersFigure 2-1 P2 and J1 Headers