Design Considerations

Reducing load capacitance will decrease output transition time, allowing for faster operation
Each buffer adds some delay; see the Switching Characteristics table in the device's data sheet
For traces longer than 12 cm (4760 mil) see Drive Transmission Lines With Logic
[FAQ] How does a slow or floating input affect a CMOS device?
[FAQ] Where do I find maximum power dissipation for a device?
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