SCPA070 june 2023 TCAL6408 , TCAL6416 , TCAL9538 , TCAL9539 , TCAL9539-Q1
Agile I/O’s offer programmable output drive strength that allows the I/O pad to be configured to one of four possible current levels. By programming the bits in the Output Drive Strength Registers, the user can adjust the number of transistor pairs that drive the I/O pad. Table 2-1 is from the TCAL6416 data sheet and describes registers 40, 41, 42, and 43 (Output Drive Strength Registers).
BIT | CC-03 | CC-03 | CC-02 | CC-02 | CC-01 | CC-01 | CC-00 | CC-00 |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
BIT | CC-07 | CC-07 | CC-06 | CC-06 | CC-05 | CC-05 | CC-04 | CC-04 |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
BIT | CC-13 | CC-13 | CC-12 | CC-12 | CC-11 | CC-11 | CC-10 | CC-10 |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
BIT | CC-17 | CC-17 | CC-16 | CC-16 | CC-15 | CC-15 | CC-14 | CC-14 |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Each P-port is assigned exactly 2 bits to configure the drive strength of the output driver. For example, P07 (which is the port 0 GPIO 7) output is configured by two bits located in register 41 called CC-07. Two configurable bits presents four different output current level options which are defined in Table 2-2. The default drive strength for an output pin is 1.00x (CC = 11).
CC – XX | Output Strength |
---|---|
00 | 0.25x |
01 | 0.5x |
10 | 0.75x |
11 | 1.00x |
The configurable bits for CC-XX determines the number of transistor pairs that are ON at a given time that feed the I/O pad. Figure 2-1 shows the PMOS/NMOS_EN devices that control the push-pull driving pairs that output on P00 – P07 and P10 – P17. Figure 2-1 is a simplified output stage of the p-port.
Reducing output drive strength has a few benefits: