SFFS059 January   2023 DRV8145-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SPI "P" variant in HTSSOP package
    2. 4.2 SPI "S" variant in VQFN-HR package
    3. 4.3 HW variant in VQFN-HR package

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for DRV8145-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
Output is stuck LOW when commanded OFF (GND short) 14%
Output is stuck HIGH when commanded OFF (VM short) 14%
Output is stuck OFF when commanded LOW (Open) 8%
Output is stuck OFF when commanded HIGH (Open) 8%
Output ON resistance too high when commanded LOW 12%
Output ON resistance too high when commanded HIGH 19%
Low side slew rate too fast or too slow (high-side recirculation) 5%
High side slew rate too fast or too slow (low-side recirculation) 5%
Dead-time is too short 1%
Current sense feedback incorrect 3%
ITRIP current regulation incorrect 3%
Incorrect communication (SPI variant)/ configuration interpretation (HW variant) 4%(1)
Incorrect input interpretation (nSLEEP, DRVOFF, IN) 3%(1)
Incorrect nFAULT assertion 1%
(1) 1% for each pin function