SFFS618 September   2024 TPS1213-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for TPS1213-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
Gate output stuck high 10
Gate output stuck low 45
Gate output functional, not in specification voltage or timing 34
Short circuit protection fails to trip or false trip5
UVLO fails to trip or false trip 1
Pin-to-pin short any two pins 5